AM62Lx is an extension of the low-power, low-cost Sitara Industrial/Auto grade family of processors. AM62Lx is based on the Cortex-A53 microprocessor, alongwith extensive peripheral and networking options for a variety of embedded applications. AM62Lx is available in a 11.9mm x 11.9mm VCA package with a mix of 0.5mm ball pitch. The package BGA design is built leveraging TI Via Channel Array Technology (VCA) technology, which enables package miniaturization while still utilizing low cost PCB routing rules. Via Channel Array (VCA) is built with careful considerations on escape routing to avoid costly High-Density Interconnect (HDI) and expensive Via technologies. This document is intended to provide a reference for escape routing on the AM62Lx device. Care must be taken to route signals with special requirements such as DDR, high speed interfaces. Refer to the High-Speed Interface Layout Guidelines and DDR Routing Guidelines for more details. Details on Power Delivery Network are provided in AM62Lx PDN Application note and any routing and layout requirements specified in those documents supersede the generic requirements provided here.

Via Channel Array Technology has been successfully used in a variety of TI products that minimizes package dimensions by using smaller ball pitch and utilizing low cost PCB routing. Via Channel technology enables routing channels to escape innermost BGA positions. This has several advantages. First, the via outside diameter (also known as the annular ring) can be larger than it normally would be if it had to be placed between the BGAs in a tighter pitch, because all the vias are placed in special areas called via channels. This makes PCB manufacturing less expensive, because larger vias are possible. Second, the vias are grouped in a radial pattern instead of a series of concentric rings around the middle of the chip, which is the case with normal BGA array PCB routing. The traces are more easily routed out of the inner parts of the chip because they are not restricted to the narrow paths between many rows of vias. The unique outer row routing and the via channel inner routing are two important parts of this technology on the AM62Lx. The AM62Lx BGA Via Channel Array is shown in Figure 2-1.

The first row (the outside row) supports any size trace desired, because the trace comes from the PCB ball land and goes out on the PCB. Normally, the second row traces must be routed in between the first row of the PCB ball lands. The AM62Lx parts allow a 3.2 mil trace/space on interior layers and 3.7 mil/4 mil trace width/space on exterior layers.

Figure 2-2 shows the first two rows of the AM62Lx package and how it is possible to route 3.2 mil traces and spaces in the areas between balls.

Starting at the third row, as with any BGA package, vias are necessary. As stated earlier, the vias are gathered in the via channels, so the only vias that need to be placed in between balls are some of the power vias in areas of ground or power copper pour. In this case, they have no regular via ring because they are located in an area of copper pour where all the surrounding balls share the same net. This is elaborated more in the later section with details on via sharing. Because the via ring is larger than one that would normally fit in between these balls with the required clearance, the layout tool may flag a design rule check (DRC) error; however, this is a false warning because there is no risk of shorting to a nearby pad as they are all on the same net. The rest of the vias must be placed into the via channels as shown below. Figure 2-3 shows how the vias are grouped in the via channels.

The AM62Lx via channel array solution has been designed to support the following. The AM62Lx package supports a similar feature set as several other competition solutions with approximately 15% smaller package area and ~10% wider line width. This solution thus reduces PCB foot print and uses lower cost PCB rules, enabling compact and low-cost systems.

PCB stack-up is one of the first and most important considerations in realizing a successful PCB. AM62Lx device supports a BGA array or 23x23 with a 0.5mm pitch and a body size of 11.9mm. PDN compliance and robustness is critical to meet all the performance objectives of the device and associated peripherals. To enable this, TI recommends allocating one layer for power planes. Ground planes must be added adjacent to the power planes and adjacent to the outer layers for shielding and controlled impedance routing. High speed interfaces such as DDR, DSI, and USB require ground planes for impedance matching. Additionally, to meet the DDR interface speeds, ground layers to reference the DDR signals are strongly recommended. The escapes on the AM62Lx board design were achieved with 6 layers, as shown below.

The AM62Lx board design example provided is implemented in a 6-layer stack-up as described above. This board is designed for optimum signal integrity on the high-speed interfaces while limiting the board size. The AM62Lx board is implemented without HDI (High Density Interconnect) and does not use micro vias, which are both intended to save board cost. All vias on the AM62Lx board are Plated Through Hole (PTH) and pass completely through the board. Additionally, via-in-pad design rules which add cost to the board are avoided. Proper analysis shall be performed to validate both signal and power integrity, if further optimizations are required to reduce PCB stack-up and/or routing rules illustrated in this document.

The Via Channel Array BGA pattern implemented on the AM62Lx design offers opportunities for via sharing. Vias are shared across BGA pins, and Figure 5-1 shows the via sharing opportunities for the GND net. Via sharing across BGA pins provides for easier escape routing and also robust electrical connection by connecting multiple pins.

Careful analysis is required to analyze the locations of the interfaces used on the device and the associated components and connectors. Optimum trace routing will have routes as short as possible with a minimum cross-over. AM62Lx offers interface selection flexibility through pin-mux choices. Pin-muxing enables a same interface function made available on multiple pins and is selectable through a pin mux option. Favorable pin-mux options that ease PCB routing and component placement can be fully used to further optimize the PCB design. The following figure shows the default arrangement of the signal balls and the power and ground balls. Priority is given to component placements without pin-mux options, such as DDR, DSI, USB, OSPI, and so forth.

Placement of the AM62Lx device and some of the components or connectors is also dictated by some of the highest performance interfaces such as DDR, DSI, and so forth. Additionally, due to the PCB losses at multi-gigabit rates, there are routing distance limits that may also limit component placement.