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The general methodology for evaluating signal integrity for high-speed SERDES interfaces is illustrated in Figure 1-1. This involves running a channel simulation for the serial link. The methodology uses IBIS-Algorithmic Modeling Interface (AMI) models for the Tx/Rx blocks. The basic setup and settings documented here can be used to validate all SerDes links and also across a variety of EDA Signal Integrity simulators. This channel simulation should be performed as a signoff check for all high-speed Serial Link interfaces.
The following things need to be kept in mind while performing channel simulation:
The serial link simulations involve a parametric sweep:
For interfaces where the eye mask is specified in terms of a BER target it is recommended to run the initial channel simulations for around 100K bits and observe the extrapolated bathtub curves for the corresponding target BER, as reported by the simulator. Another simulation for around 500K and 1M bits can be rerun and the bathtub curves can be overlaid to observe the impact of running for larger bit sequences. An example of voltage bathtub curves overlaid is shown in Figure 1-3). Similar overlay can be made for the jitter bathtub curves.
Typically, all the ISI should be accounted for within the first 100K bits of the simulation and beyond this point, all bathtub curves should converge if the Random Jitter (Rj) in the models is sufficiently small. It is recommended to confirm this convergence up front by running at least one set of system-level channel simulations each for 100K, 500K and 1M bit sequences. If the voltage and jitter bathtub curves from each of these simulations are almost identical, the remainder of the simulations can be run at 100K bits to optimize run times.
For interfaces where the eye mask is not specified for any particular BER target, a 100K bit simulation should suffice.