The general methodology for evaluating signal integrity for high-speed SERDES interfaces is illustrated in Figure 1-1. This involves running a channel simulation for the serial link. The methodology uses IBIS-Algorithmic Modeling Interface (AMI) models for the Tx/Rx blocks. The basic setup and settings documented here can be used to validate all SerDes links and also across a variety of EDA Signal Integrity simulators. This channel simulation should be performed as a signoff check for all high-speed Serial Link interfaces.

Figure 1-1 Signal Integrity Analysis Setup - Channel Simulation

The following things need to be kept in mind while performing channel simulation:

• Odd mode crosstalk is used to define aggressor and victim switching in opposite directions. This is required if multiple lanes are simulated.
• An important note to keep in mind is that the jitter and noise of Tx/Rx blocks should not be double counted. As the IBIS-AMI models already have the various jitter sources incorporated, the option to include additional jitter in these blocks must be turned off in the EDA simulation engine of choice.

The serial link simulations involve a parametric sweep:

• Corners: The IBIS-AMI models for Tx/Rx are characterized as Fast/Typ/Slow corners. The different Deterministic and Random Jitter budgets are built in to the models using these corners.
• Transmitter Presets: These are specific to each standard and control the coefficients in the transmitter Decision Feedback Equalizer (DFE). These presets also model the level of de-emphasis in the transmit amplifier which are required to equalize the overall system-level response across different frequencies and counteract the impact of ISI (Inter-symbol interference). It is recommended using a parametric sweep and simulate for all different transmitter presets for a given Serial Link protocol. This is due to the fact that the best eye observed can be highly dependent on the system impulse response and therefore different presets could yield the best results on different systems.
• Data Patterns: It is recommended to use PRBS23 or PRBS31 patterns to validate the system, in order to excite larger levels of ISI.
• LIBPATH Definition: Ensure that the “LIBPATH” variable in the Rx IBIS-AMI model is set correctly, to point to the local data directory, which points to the Rx CTLE files as shown in Figure 1-2. The name of this variable might change from simulator to simulator. However, the directory always needs to point to the local copy.

Figure 1-2 LIBPATH Definition

For interfaces where the eye mask is specified in terms of a BER target it is recommended to run the initial channel simulations for around 100K bits and observe the extrapolated bathtub curves for the corresponding target BER, as reported by the simulator. Another simulation for around 500K and 1M bits can be rerun and the bathtub curves can be overlaid to observe the impact of running for larger bit sequences. An example of voltage bathtub curves overlaid is shown in Figure 1-3). Similar overlay can be made for the jitter bathtub curves.

Figure 1-3 Bathtub Curve Overlay

Typically, all the ISI should be accounted for within the first 100K bits of the simulation and beyond this point, all bathtub curves should converge if the Random Jitter (Rj) in the models is sufficiently small. It is recommended to confirm this convergence up front by running at least one set of system-level channel simulations each for 100K, 500K and 1M bit sequences. If the voltage and jitter bathtub curves from each of these simulations are almost identical, the remainder of the simulations can be run at 100K bits to optimize run times.

For interfaces where the eye mask is not specified for any particular BER target, a 100K bit simulation should suffice.

The results generated by the channel simulations outlined in the preceding sections are compared against an eye mask spec. This eye mask is summarized in Table 1-1. This is used as a pass/fail check for the system

The IBIS – AMI Model Kit provides the IBIS/AMI models corresponding to 16nm PHY from the Cadence IP team. The kit models the transmitter for various FFE combinations and receiver for peak amp, VGA, attenuator, DFE and CDR. It also models the back channel, provided the simulation tool supports it.

Figure 2-1 is a snapshot of the structure of the model kit.

Figure 2-1 Structure of the Models Kit

The IBIS-AMI models provided in the kit represent the Torrent16FFC TSMC 16 nm PHY from Cadence Design Systems.

As per the IBIS-AMI specification, the algorithmic model and channel simulator executable must be compiled for the same hardware platform to work. For more information, see the IBIS specification at http://www.eda.org/ibis/ver5.1/.

This IBIS-AMI Model Kit has been tested with the Allegro Sigrity SystemSI product from Cadence Design Systems, Inc.

The IBIS analog models provided in the kit in the file “torrent16_gen<1/2/3>.ibs” include:

• Transmitter (Tx) IO model“torrent16_driver”
• Receiver (Rx) IO model“torrent16_receiver”