Enabling Peripheral Expansion Applications Using the HIC

C2000™ microcontrollers offer several differentiated peripherals, enabling real-time control intensive industrial and digital power applications. The Host Interface Controller (HIC) allows an external application controller to take advantage of the C2000’s differentiated peripherals and processing capabilities through a commonly supported Asynchronous interface. For instance, the Fast Serial Interface (FSI) is capable of supporting low-latency and robust high-speed communication across isolation in a system. Using the HIC, any application processor can integrate FSI on to their system to perform high speed communication over isolation. This application report introduces example HIC applications and helps to select the right configuration of the HIC peripheral as per the application requirements.

You are expected to be familiar with the HIC chapter of an applicable C2000 Device's Technical Reference Manual (TRM), which covers the complete feature set and register definitions.

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1 Introduction

The Host Interface Controller (HIC) provides an asynchronous interface through which an external Host processor can access most of the C2000 device's peripherals.

NOTE

This document includes HIC usage examples using the F28002x Device, but the concepts also apply to other C2000 devices that support the HIC. Throughout the document, the designation of “Host” will refer to the external Host processor, while the designation of “Device” will refer to the Device with support for the HIC.

Through the HIC, the Host can use the Device as a peripheral expander, by taking advantage of the C2000’s differentiated features. For example, Figure 1 shows how the Host with an Asynchronous RAM interface can use the Device as a peripheral bridge for high-speed communication across isolation using the FSI.

Figure 1. HIC Bridge for FSI Applications

Another application of the HIC could be to take advantage of the Configurable Logic Block (CLB) peripheral that is available with the C2000 family of devices. The CLB enables custom logic implementation and augments the existing C2000 peripheral set, thereby eliminating or reducing the need for FPGA, CPLD, or external logic components to achieve the same results. There are numerous solutions that can be implemented with the CLB, one of which is the absolute encoder protocol implementation to interface with the position sensors in an industrial drive control system. For the encoder protocols that are supported by the CLB, see the Position manager technology. The HIC can be used as a bridge for the Host to interface with the position sensors as shown in Figure 2.

spracr2-hic-bridge-for-position-encoder-applications.gif

Figure 2. HIC Bridge for Position Encoder Applications

In a similar fashion, F28002x can be used as a motor controller by the Host taking advantage of the peripherals like PWMs, ADCs and CMPSS. Position reference data can be sent from the Host to the F28002x and the feedback data like motor current, present position can be accessed via ADC.

Figure 3. HIC Bridge for Motor Control Applications

HIC applications are not just limited to peripheral expansion; the Host can offload math intensive computations to the C2000 Device whose enhanced instruction set can be leveraged to increase the system performance in real-time applications. To know about different performance enhanced instruction sets and accelerators supported by C2000 family of devices, see the Accelerators: Enhancing the Capabilities of the C2000 MCU Family Technical Brief.

2 HIC Configurations Overview

The HIC supports a variety of configurations with which the Host can be connected. Each configuration has certain advantages and implications with respect to latency, input/output (I/O) pin overheads and so on. For a full overview of the HIC features, see the HIC chapter of the device-specific technical reference manual. This section deals with the various configurations and serves as a guide in selecting the right configuration according to the system requirements.

2.1 Access Modes

The HIC supports two access modes through which the Host can access the Device peripherals:

Mailbox access mode
Direct access mode

For the configuration details and the programming sequences for each of these usage models, see the HIC chapter of the device-specific Technical Reference Manual.

In the direct access mode, the Host CPU can directly access the memory map of the accessible peripheral in the Device; the Host access to the peripheral does not need Device CPU intervention once configured.

In Mailbox access type, the Host access is limited to the HIC’s registers and any access to the peripheral should be facilitated via the Device’s CPU or DMA to transfer data between the peripheral registers and HIC mailboxes.

Mailbox accesses have the advantage of fixed and lower latency when compared to the direct accesses to the peripherals. This is due to the fact that Host accesses in direct access mode are routed through the Device Bus-Interconnects which may arbitrate with CPU and DMA within the device.

2.2 Data Width Selection

Support for 8-bit and 16-bit HIC data width modes is controlled via the HICMODECR.DW_MODE register field. In order to perform a 32-bit access, the Host has to initiate four accesses in 8-bit mode, while two accesses are sufficient in the case of 16-bit mode as shown in Table 1. This gives 16-bit data width mode an advantage over the 8-bit mode in terms of raw throughput at the cost of incurring 8 additional I/O pins for data.

Table 1. Host Transaction for Different Data-Width Modes

Intended Write by the Host	Data Width Mode	Write cycle1	Write cycle2	Write cycle3	Write cycle4
Address = 0x5000 Data = 0x12345678	16 bits	HICDBADDR0 = 0x5000 HIC_A[7:0] ⁽¹⁾ = 0x0 HIC_D[15:0] = 0x5678	HICDBADDR0 = 0x5000 HIC.A[7:0] = 0x1 HIC.D[15:0] = 0x1234	-	-
Address = 0x5000 Data = 0x12345678	8 bits	HICDBADDR0 = 0x5000 HIC.A[7:0] = 0x0 HIC.D[15:0] = 0x78	HICDBADDR0 = 0x5000 HIC.A[7:0] = 0x1 HIC.D[15:0] = 0x56	HICDBADDR0 = 0x5000 HIC.A[7:0] = 0x2 HIC.D[15:0] = 0x34	HICDBADDR0=0x5000 HIC.A[7:0] = 0x3 HIC.D[15:0] = 0x12

Fields in italics are I/O pins.

The address translation for different data width modes is covered in detail in Section A.