This user’s guide defines the power distribution network (PDN) between the TPS6594-Q1 and LP8764-Q1 devices and the DRA821 processor. This document describes the platform power resource connections, digital control connections, and PMIC sequencing settings to support the different processor state transitions. The PMIC default non-volatile memory (NVM) settings, internal state transitions, and power sequences are also defined in this document. This user's guide does not provide information about the electrical characteristics, external components, package, or the functionality of the PMICs or processor. For such information and the full register maps, refer to the data sheet for each device. In the event of any inconsistency between the official specification and any user's guide, application report, or other referenced material, the data sheet specification is the definitive source.

There are different versions of the TPS6594-Q1 and LP8764-Q1 devices available with unique NVM settings to support different processor solutions. The unique NVM settings for each PMIC device are optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features - such as low power modes, processor interface levels, SD Card, and so forth. The NVM settings can be distinguished using the TI_NVM_ID register. In this user guide, each PMIC device is distinguished by the TI orderable part number, TI_NVM_ID, and TI_NVM_REV values listed in Table 2-1.

This section details how the TPS6594-Q1 and LP8764-Q1 power resources and GPIO signals are connected to the processor and other peripheral components to support the PDN use case.

Figure 3-1 shows the detailed power mapping between the processor and the TPS6594-Q1 and LP8764-Q1 PMICs. In this configuration, both PMICs use a 3.3 V input voltage. For Functional Safety applications, there is a protection FET before VCCA that connects to the OVPGDRV pin of the primary PMIC, allowing voltage monitoring of the input supply to the PMICs.

The VCCA voltage must be the first voltage applied to the PMIC devices. VIO_IN of the PMICs must be supplied after VCCA. In this configuration, VIO_IN is supplied by the load switch that also supplies the VDDSHVx_MCU voltage domain of the processor to allow the digital components of the PMIC devices (such as GPIOs) to remain supplied in MCU-only mode. Additionally, by controlling VIO_IN of both PMICs through this load switch, the system can also reduce power consumption in GPIO Retention or DDR Retention modes, since the load switch is disabled.

This PDN supports the use of either a single dual load switch (TPS22966-Q1) with an AEC-100 Grade 2 (-40 to +105°C) temperature rating or two single load switches (TPS22965-Q1) with an AEC-100 Grade 1 (-40 to +125°C) rating if a higher ambient temperature range is desired. The PDN diagrams of this section also include a few optional discrete power components to support additional system functions that may be needed. The TLV70033-Q1 LDO is used to support compliant USB data eye performance by supplying a low noise 3.3 V for USB 2.0 interface integration. The TLV70018-Q1 LDO is available to support on-board EFUSE programming on high security SoC PNs. Alternative LDOs can be chosen for SD card dual-voltage I/O support (3.3 V and 1.8 V), TLV7103318-Q1 dual-voltage LDO can be used to enable compliant, dual voltage, high-speed SD card operations.

The power resource assignments shown in Figure 3-1 enable the support for different processor low-power modes, including MCU-only mode, GPIO Retention, and DDR Retention. Please use Table 3-1 as a guide to understand which power resources are required to support different system features. If the system feature listed is not required, the power resource connection can be removed.

Figure 3-2 shows the digital control signal mapping between the processor and the PMIC devices. For the two PMIC devices to work together, the primary PMIC and secondary PMIC must establish an SPMI communication channel. The SPMI bus allows the TPS6594-Q1 and LP8764-Q1 to synchronize their internal Pre-Configurable State Machines (PFSM) so that they operate as one PFSM across all power and digital resources. The GPIO_5 and GPIO_6 pins on the TPS6594-Q1 and GPIO_8 and GPIO_9 pins on LP8764-Q1 are assigned for this functionality. In addition, the LDOVINT pin of the primary PMIC must be connected to the ENABLE input (GPIO_4 of LP8764-Q1) of the secondary PMIC to correctly initiate the PFSM.

Other digital connections from the TPS6594-Q1 devices to the processor allow support for error monitoring, processor reset, processor wake up, and system low-power modes. Specific GPIO pins have been assigned to key signals in order to ensure proper operation during low power modes when only a few GPIO pins remain operational.

To support DDR retention low power mode, the following PMIC GPIO functions are required:

1. GPIO_2 and GPIO_3 of LP8764-Q1 connected to an external, low voltage latch to create a sustained control signal to DDR_RET of the processor. The latch is needed since the PMIC VIO_IN power rail supplying GPIO_2 and 3 is disabled during DDR Retention state.
2. Sustained GPIO_9 of TPS6594-Q1 connected to the enable input of a 3.3V in-line load switch to the MCU.
3. Sustained GPIO_4 of TPS6594-Q1 with NVM default function set as LP_WKUP1 and mask bit set high to avoid false triggering until CAN wakeup signal is armed. SW must properly arm CAN PHY so that wakeup signal is set high and unmask GPIO_4 before entering GPIO Retention state.

To support GPIO retention low power mode, the following PMIC GPIO functions are required:

1. Sustained GPIO_7 of LP8764-Q1 connected to the enable input of an in-line load switch to control the 3.3 V GPIO retention domain.

Additional digital options also include GPIO_10 of TPS6594-Q1, which can be configured by software as a 32 kHz clock output for the processor oscillator input (LFOSC ). There is also the option to disable the watchdog timer using hardware, by pulling GPIO_8 of TPS6594-Q1 high. Lastly, GPIO_1 of LP8764-Q1 is included in the power up sequence to enable external regulators, for options such as DDR I/O.

The digital connections shown in Figure 3-2 allow system features including MCU-only mode, GPIO retention mode, DDR retention mode, and functional safety systems capable of supporting up to ASIL-D. Please use Table 3-2 as a guide to understand GPIO assignments required for these features. If the feature listed is not required, the digital connection can be removed. For details on how functional safety related connections help achieve functional safety system-level goals, see Section 4.

By using the TPS6594-Q1 and LP8764-Q1 solution to power the DRA821 processor, the system can leverage the following PMIC functional safety features:

• Independent Power Control of MCU and Main Rails
• Independent Monitoring and Reset for MCU and Main Rails
• Input Supply Monitoring
• Output Voltage and Current Monitoring
• Question & Answer Watchdog
• Fault Reporting Interrupts
• Enable Drive Pin that provides an independent path to disable system actuators
• Error Pin Monitoring
• Internal Diagnostics including voltage monitoring, temperature monitoring, and Built-In Self-Test

Refer to the Safety Manuals of the TPS6594-Q1 and LP8764-Q1 devices for full descriptions and analysis of the PMIC functional safety features. These functional safety features can assist in achieving up to ASIL-D rating for a system. Additionally, these features help in achieving the functional safety assumptions utilized by the processor to achieve up to ASIL-D rating. See the DRA821 Safety Manual for Jacinto™ 7 Processors for a complete list of functional safety system assumptions.

To achieve a system functional safety level of ASIL-B, the following PDN features are available:

• PMIC over voltage and under voltage monitoring on the power resource voltage outputs
• PMIC over-voltage monitoring and protection on the input to the PMIC (VCCA)
• Watchdog monitoring of safety processor
• MCU error monitoring
• MCU reset
• I2C communication
• Error indicator, EN_DRV, for driving external circuitry (optional)
• Read-back of EN_DRV pin

The PDN has an in-line, external power FET between the input supply and PMICs. This FET can quickly isolate the PMICs when an over-voltage event greater than 6 V is detected on the input supply to protect the system from being damaged, as shown in Figure 3-1. Note that any power rail connected after the FET can be protected from an over voltage event. Any power connected upstream from the FET is not protected from over voltage events. In Figure 3-1 the load switches that supply power to the MCU and Main I/O domains and the discrete buck supplying the DDR are all connected after the FET to extend the over voltage protection to these processor domains and discrete power resources.

The PMIC internal over voltage and under voltage monitoring and their respective monitoring threshold levels can be enabled through I2C after startup. To monitor the load switch voltage that supplies the MCU I/O of the processor, it is recommended to use the processor POK monitor built into the VDDSHV0_MCU voltage domain.

The PMIC Internal Q&A Watchdog is enabled by default on the TPS6594-Q1 device. Once the device is in ACTIVE state, the trigger or Q&A watchdog settings can be configured through the secondary I2C in the device. The steps for configuring the watchdog settings can be found in the TPS6594-Q1 data sheet. Setting the DISABLE_WDOG signal high on TPS6594-Q1 GPIO_8 disables the watchdog timer if this feature needs to be suspended or is not required in the system.

GPIO_7 of the TPS6594-Q1 PMIC is configured as the MCU error signal monitoring, and must be enabled though the ESM_MCU_EN register bit. MCU reset is supported through the connection between the primary PMIC nRSTOUT pin and the MCU_PORz of the processor. Lastly, there are 2 I2C ports between the TPS6594-Q1 and the processor. The first is used for all non-watchdog communication, such as voltage level control, and the second allows the watchdog monitoring to be on an independent communication channel.

There is an option to use the EN_DRV of theTPS6594-Q1 PMIC to indicate an error has been detected and the system is entering SAFE state. This signal can be utilized if the system has some additional external circuitry that needs to be driven by an error event. In this PDN, the EN_DRV is not utilized, but available if needed.

For ASIL-C or ASIL-D systems, there are additional features to the ones described in Section 4.1 that can be utilized. These features include:

• PMIC current monitoring on all output power rails
• Isolation of the MCU and Main power domains of the processor
• SoC reset

The current monitoring is enabled by default for all BUCKs and LDOs for the TPS6594-Q1 and LP8764-Q1 devices. Additionally, Figure 3-1 shows that the MCU domain of the processor is powered by different power resources of the PMICs than the main power domain of the processor. SoC reset functionality is supported through the connection of GPIO_11 on TPS6594-Q1, configured as nRSTOUT_SoC, to the PORz pin of the processor.

The TPS6594-Q1 and LP8764-Q1 devices consist of fixed registers and configurable registers that are loaded from the NVM. For all NVM registers, the initial NVM settings that load into the registers are provided in this section. Note that these initial NVM settings can be changed during state transitions, such as moving from STANDBY to ACTIVE mode. The full register map, including default values of fixed registers, is located in the corresponding PMIC data sheet. Empty values indicate that the device does not have the register included. For example, LP8764-Q1 does not have BUCK5 registers at all and therefore the values for it are empty.

In the LP876441B1-Q1 and TPS6594141B-Q1 data sheet, there are multiple application-based configurations for each BUCK to operate within. Table 5-1 includes the different configurations available:

The seven configurations also have optimal output inductance values that optimize the performance of each buck under these various conditions. Table 5-2 shows the default configurations for the BUCKs. These settings cannot be changed after device startup.