This document is the EVM user’s guide for the TMUXRUM-RRPEVM, which provides a quick way to evaluate TI devices that use a 16-pin RUM or RRP package.
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This user's guide describes the TMUXRUM-RRPEVM evaluation module (EVM) and its intended use. This board allows for the quick prototyping and DC characterization of TI’s line of TMUX products that use 16-pin QFN packages (RUM or RRP).
Always follow TI’s setup and application instructions, including use of all interface components within their recommended electrical rated voltage and power limits. Always use electrical safety precautions to help ensure your personal safety and those working around you. Contact TI's Product Information Center http://support/ti./com for further information.
Save all warnings and instructions for future reference.
The term TI HV EVM refers to an electronic product typically provided as an open framed, unenclosed printed circuit board assembly. It is intended strictly for use in development laboratory environments, solely for qualified professional users having training, expertise and knowledge of electrical safety risks in development and application of high voltage electrical circuits. Any other use or application are strictly prohibited by Texas Instruments. If you are not suitably qualified, you should immediately stop from further use of the HV EVM.
Limitation for safe use:
EVMs are not to be used as all or part of a production unit.
The information in the warning statement is provided for personal protection and the information in the caution statement is provided to protect the equipment from damage. Read each caution and warning statement carefully.
The TMUXRUM-RRPEVM has the following features:
Selectable thermal pad connection
There are 16 headers located around the board with designators J1 through J16. These 3-by-2 headers serve as connections to power planes and to signals of the DUT (U1). Each pin of the DUT has similar header and test point configuration. At four different locations around the board, a legend shows the connections of the pins of the nearby four headers. Figure 5-1 shows a representation of the header associated with pin 1 of U1.
The silkscreen legend represents the connections of the pins of J1. Figure 5-2 shows the pin numbers of this header from this same perspective.
Table 5-1 also shows the connections.
Header pin number | Connection |
---|---|
1 | No connection |
2 | VDD |
3 | GND |
4 | U1 |
5 | GND |
6 | VSS |
For all headers J1 through J16, the connections are the same, but are rotated by a multiple of 90° according to their position on the board. A legend is included for each rotation.
There is one 3-by-1 header located near the DUT (J17). Pin 2 of this header is connected to the thermal pad of the DUT. Pin 1 of this header is connected to GND, and pin 3 of this header is connected to VSS.
The connections of J17 are also labeled on the board’s silkscreen layer next to the header.
In addition to headers, multiple test points are located around the board. Black test points (TP18 and TP20-TP26) are connected to GND, the red test point (TP17) is connected to VDD, and the green test point (TP19) is connected to VSS. The remaining blue test points (TP1-TP16 and TP101-TP116) are connected along the signal paths of the pins of U1.
The last two digits of the blue test point number represent the pin with which the test point is associated. For example, TP16 and TP116 are both pin 16 of U1.
Table 5-2 shows the test point connections.
Designator | Connection |
---|---|
TP1 | J1.4 |
TP2 | J2.4 |
TP3 | J3.4 |
TP4 | J4.4 |
TP5 | J5.4 |
TP6 | J6.4 |
TP7 | J7.4 |
TP8 | J8.4 |
TP9 | J9.4 |
TP10 | J10.4 |
TP11 | J11.4 |
TP12 | J12.4 |
TP13 | J13.4 |
TP14 | J14.4 |
TP15 | J15.4 |
TP16 | J16.4 |
TP17 | VDD |
TP18 | GND |
TP19 | VSS |
TP20 | GND |
TP21 | GND |
TP22 | GND |
TP23 | GND |
TP24 | GND |
TP25 | GND |
TP26 | GND |
TP101 | U1.1 |
TP102 | U1.2 |
TP103 | U1.3 |
TP104 | U1.4 |
TP105 | U1.5 |
TP106 | U1.6 |
TP107 | U1.7 |
TP108 | U1.8 |
TP109 | U1.9 |
TP110 | U1.10 |
TP111 | U1.11 |
TP112 | U1.12 |
TP113 | U1.13 |
TP114 | U1.14 |
TP115 | U1.15 |
TP116 | U1.16 |
Terminal block J35 is the power input for the board. Three power rails (VSS, GND, and VDD) are labeled on the board’s silkscreen layer, indicating the identities of the input pins of the header. Connect the power supply rails at this terminal block to power the board.
The TMUXRUM-RRPEVM will not have any device connected at footprint U1, and no devices are included with the EVM for this footprint. Attach any compatible Texas Instruments 16-pin TMUX device to this location, which will serve as the Device Under Test (DUT). Compatible devices include parts with RUM or RRP package names.
By default, the TMUXRUM-RRPEVM will have shunts on headers J1 through J16 connected such that the pins of U1 are connected to GND. Remove these shunts from J1 through J16 as necessary if these connections are not desired. Alternatively, the pins of U1 can be shorted to VDD or VSS by connecting between pin 4 of the header and one of the other pins on the header. Figure 5-2 and Table 5-1 includes detailed descriptions of the connections on J1 through J16.
As shown in Figure 6-2 and Figure 6-3 as R5 and R6 on the J1 (pin 1 of U1) signal line, the TMUXRUM-RRPEVM includes 0 Ω series resistors (0805 package) on each signal line.
These can be substituted for different resistors as desired. Additionally, there are pads for pull-up and pull-down resistors to VDD and GND respectively. Add any 0603 resistor to the footprint shown as R1 to provide pull-up to VDD, and add any 0603 resistor to the footprint shown as R13 to provide pull-down to GND.
Each signal line also includes two footprints that allow for the user to attach capacitors or other devices with matching footprints. On the top side of the board, shown in Figure 6-2 and Figure 6-3 as C1, a standard 1206 footprint exists between the U1 pin signal and the GND signal. The user can solder a capacitor to this footprint to provide capacitance to the signal line.
Figure 6-4 shows that a standard 1812 footprint exists as C101 on the backside of the board, which also allows a capacitor to be connected between the U1 pin signal and GND. The user can solder a capacitor to this footprint to provide capacitance to the signal line.
The user has the ability to select the connection of the thermal pad of U1 by using the three-by-one header located near U1 (J17).
Connecting a shunt between pins 1 and 2 of this header will tie the thermal pad of U1 to GND, while connecting pins 2 and 3 will tie the thermal pad of U1 to VSS. Leave pin 2 of this header unconnected to allow the thermal pad to float, or use an external connection to tie the thermal pad to any other potential.
Figure 7-1 shows the layout of the EVM PCB.
Figure 8-1 and Figure 8-2 are schematic views of the TMUXRUM-RRPEVM that includes all the parts and connections.
Figure 8-3 and Figure 8-4 are schematic views of the TMUXRUM-RRPEVM that show only the parts that are included in the EVM and excludes the parts that are DNI.