ZHCSTF0C February   2019  – August 2024 TUSB2E22

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Requirements
  7. 6 Parametric Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 2.0
      2. 7.3.2 eUSB2
      3. 7.3.3 Cross MUX
    4. 7.4 Device Functional Modes
      1. 7.4.1 Repeater Mode
      2. 7.4.2 Power Down Mode
      3. 7.4.3 CROSS
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Dual Port System Implementation
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up Reset
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Example YCG Layout For Application With No Cross MUX Function.
      3. 8.4.3 Example RZA Layout For Application With No Cross MUX Function
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TUSB2E22 YCG Package, 25-Pin DSBGA (Top View) Figure 4-1 YCG Package, 25-Pin DSBGA (Top View)
Legend
3.3 V Rails 1.8 V Rails eUSB2 Data Signals
USB2 Data Signals GPIO Digital Input or Output
Table 4-1 Pin Functions
PIN TYPE RESET STATE ASSOCIATED ESD SUPPLY DESCRIPTION
NO. NAME
B2, D2 VDD3V3 PWR N/A N/A 3.3 V Supply Voltage
C3, B4, D4 VDD1V8 PWR N/A N/A 1.8 V Analog Supply Voltage
C1, C4, B3, D3, C5 VSS GND N/A N/A GND
E4 RESETB Digital Input N/A VDD1V8 Active Low Reset. Upon deassertion of RESETB both repeaters will be enabled and be in eUSB2 default mode awaiting configuration from eDSPr or eUSPr.
C2 CROSS Digital Input N/A VDD3V3 Indicates mux orientation. Used to specify orientation of internal Crossbar switch
CROSS = Low: eUSB0 «–» USBA and eUSB1 «–» USBB
CROSS = High: eUSB0 «–» USBB and eUSB1«–» USBA
Sampled at deassertion of RESETB
A2 RSVD1 Digital I/O Hi-Z VDD3V3 Reserved pins connect 1 kΩ pull up to 1.8 V
A3 RSVD2 Digital I/O Hi-Z VDD3V3 Reserved pins connect 1 kΩ pull up to 1.8 V
A4 RSVD3 Digital Output Hi-Z VDD3V3 Reserved pin leave it unconnected
E2 EQ0 Digital I/O Hi-Z (input) VDD3V3 Compensation Level 0: EQ1=low EQ0= low
Compensation Level 1: EQ1=low EQ0=high
Compensation Level 2: EQ1=high EQ0=low
Compensation Level 3: EQ1=high EQ0=high
Pins are sampled at RESETB deassertion
E3 EQ1 Digital I/O Hi-Z (input) VDD3V3
A1 eDP0 Analog I/O Hi-Z VDD1V8 eUSB2 port 0 D+ pin
B1 eDN0 Analog I/O Hi-Z VDD1V8 eUSB2 port 0 D- pin
D1 eDN1 Analog I/O Hi-Z VDD1V8 eUSB2 port 1 D- pin
E1 eDP1 Analog I/O Hi-Z VDD1V8 eUSB2 port 1 D+ pin
A5 DPA Analog I/O Hi-Z VDD3V3 USB port A D+ pin
B5 DNA Analog I/O Hi-Z VDD3V3 USB port A D- pin
D5 DNB Analog I/O Hi-Z VDD3V3 USB port B D- pin
E5 DPB Analog I/O Hi-Z VDD3V3 USB port B D+ pin
TUSB2E22 0.5-mm Pitch RZA Package, 20-Pin VQFN (Top View) Figure 4-2 0.5-mm Pitch RZA Package, 20-Pin VQFN (Top View)
Table 4-2 Pin Functions
PIN TYPE(1) RESET STATE ASSOCIATED ESD SUPPLY DESCRIPTION
NAME NO.
VDD3V3 15 PWR N/A N/A 3.3 V supply voltage
VDD1V8 3, 11 PWR N/A N/A 1.8 V analog supply voltage
GND 8, 18, Thermal Pad (21), Corner Anchors (A, B, C, D) GND N/A N/A GND
RESETB 5 Digital Input N/A VDD1V8 Active Low Reset. Upon deassertion of RESETB both repeaters will be enabled and be in eUSB2 default mode awaiting configuration from eDSPr or eUSPr.
CROSS 1 Digital Input N/A VDD3V3 Indicates mux orientation. Used to specify orientation of internal Crossbar switch
CROSS = Low: eUSB0 «–» USBA and eUSB1 «–» USBB
CROSS = High: eUSB0 «–» USBB and eUSB1«–» USBA
Sampled at deassertion of RESETB
RSVD1 14 Digital I/O Hi-Z VDD3V3 Reserved pins connect 1 kΩ pull up to 1.8 V
RSVD2 13 Digital I/O Hi-Z VDD3V3 Reserved pins connect 1 kΩ pull up to 1.8 V
RSVD3 12 Digital Output Hi-Z VDD3V3 Reserved pin leave it unconnected
EQ0 2 Digital I/O Hi-Z (input) VDD3V3 Compensation Level 0: EQ1=low EQ0= low
Compensation Level 1: EQ1=low EQ0=high
Compensation Level 2: EQ1=high EQ0=low
Compensation Level 3: EQ1=high EQ0=high
Pins are sampled at RESETB deassertion
EQ1 4 Digital I/O Hi-Z (input) VDD3V3
eDP0 16 Analog I/O Hi-Z VDD1V8 eUSB2 port 0 D+ pin
eDN0 17 Analog I/O Hi-Z VDD1V8 eUSB2 port 0 D- pin
eDN1 19 Analog I/O Hi-Z VDD1V8 eUSB2 port 1 D- pin
eDP1 20 Analog I/O Hi-Z VDD1V8 eUSB2 port 1 D+ pin
DPA 10 Analog I/O Hi-Z VDD3V3 USB port A D+ pin
DNA 9 Analog I/O Hi-Z VDD3V3 USB port A D- pin
DNB 7 Analog I/O Hi-Z VDD3V3 USB port B D- pin
DPB 6 Analog I/O Hi-Z VDD3V3 USB port B D+ pin
(1) PWR = power, GND = ground, I = input, O = output