Data Sheet
TPS7H60x3-SP 耐辐射保障 1.3A、2.5A、
半桥 GaN FET 栅极驱动器
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1 特性
- 辐射性能：
- 耐辐射保障 (RHA) 高达
100krad(Si) 总电离剂量 (TID) - 单粒子锁定 (SEL)、单粒子烧毁 (SEB) 和单粒子栅穿 (SEGR) 对于线性能量传递 (LET) 的抗扰度高达 75MeV-cm2/mg
- 单粒子瞬变 (SET) 和单粒子功能中断 (SEFI) 的特征值高达 LET = 75MeV-cm2/mg
- 耐辐射保障 (RHA) 高达
- 1.3A 峰值拉电流和 2.5A 峰值灌电流
- 两种工作模式：
- 具有可调死区时间的单个 PWM 输入
- 两个独立输入
- 在独立输入模式下提供可选输入互锁保护
- 分离输出实现可调的导通和关断时间
- 独立输入模式下的典型传播延迟为 30ns
- 5.5ns 典型延迟匹配
3 说明
TPS7H60x3-SP 系列耐辐射保障 (RHA) 氮化镓 (GaN) 场效应晶体管 (FET) 栅极驱动器专为高频、高效率应用而设计。该系列包括 TPS7H6003-SP（200V 等级）、TPS7H6013-SP（60V 等级）和 TPS7H6023-SP（22V 等级）。这些驱动器具有可调节死区时间功能、30ns 低传播延迟，以及 5.5ns 的高侧和低侧匹配。这些器件还包括内部高侧和低侧 LDO，无论电源电压如何，都能确保驱动电压为 5V。TPS7H60x3-SP 驱动器都具有分离栅输出，可独立灵活地调节输出的导通和关断强度。
TPS7H60x3-SP 驱动器具有两种控制输入模式：独立输入模式 (IIM) 和 PWM 模式。在 IIM 中，每个输出都由专用输入来控制。在 PWM 模式下，两个补偿输出信号由单个输入产生，用户可以调节每个边沿的死区时间。
栅极驱动器还提供用户可配置的输入互锁功能，在独立输入模式下作为防击穿保护。当两个输入同时导通时，输入互锁不允许两个输出同时导通。用户可以选择在独立输入模式下启用或禁用此保护，从而可以在多种不同的转换器配置中使用该驱动器。这些驱动器还可用于半桥和双低侧转换器应用。
器件信息
| 器件型号(1) | 等级 | 本体尺寸(2) |
|---|---|---|
| 5962R2220101VXC | QMLV-RHA | 48 引脚陶瓷 8.48 × 16.74mm 质量 = 2.212g(3) |
| 5962R2220102VXC | ||
| 5962R2220103VXC(4) | ||
| TPS7H6003HBX/EM | 工程样片 | |
| TPS7H6013HBX/EM | ||
| TPS7H6023HBX/EM(4) |
(1) 有关更多信息，请查看器件选项 表。
(2) 本体尺寸（长 × 宽）为标称值，不包括引脚。
(3) 质量为标称值。
(4) 产品预发布。
4 Device Comparison Table
| DEVICE | ABSOLUTE MAXIMUM VOLTAGE (1) | RECOMMENDED OPERATING VOLTAGE(1) |
|---|---|---|
| TPS7H6003-SP | 200 V | 150 V |
| TPS7H6013-SP | 60 V | 45 V |
| TPS7H6023-SP(2) | 22 V | 14 V |
(1) This represents the "SW to GND"
voltage rating of the devices as shown in the Specifications section.
(2) Product preview.
5 Device Options Table
| GENERIC PART NUMBER | RADIATION RATING(1) | GRADE(2) | PACKAGE | ORDERABLE PART NUMBER |
|---|---|---|---|---|
| TPS7H6003-SP | TID characterization up to 100 krad(Si) and DSEE free up to LET = 75 MeV-cm2/mg | QMLV-RHA | 48-pin ceramic flatpack (CFP) HBX | 5962R2220101VXC |
| None | Engineering sample(3) | TPS7H6003HBX/EM | ||
| TPS7H6013-SP | TID characterization up to 100 krad(Si) and DSEE free up to LET = 75 MeV-cm2/mg | QMLV-RHA | 5962R2220102VXC | |
| None | Engineering sample(3) | TPS7H6013HBX/EM | ||
| TPS7H6023-SP | TID characterization up to 100 krad(Si) and DSEE free up to LET = 75 MeV-cm2/mg | QMLV-RHA | 5962R2220103VXC(4) | |
| None | Engineering sample(3) | TPS7H6023HBX/EM(4) | ||
| SN0048HBX | N/A | Mechanical "dummy" package (no die) | SN0048HBX |
(1) TID is total ionizing dose and
DSEE is destructive single event effects. Additional information is available
in the associated TID and SEE radiation reports for the device.
(2) For additional information about
part grade, view SLYB235.
(3) These units are intended for
engineering evaluation only. They are processed to a non-compliant flow (such as
no burn-in and only 25°C testing). These units are not suitable for
qualification, production, radiation testing, or flight use. Parts are not
warranted for performance over temperature or operating life.
(4) Product preview.
6 Pin Configuration and Functions
Figure 6-1 HBX Package48-Pin CFP
(Top View)
Pin
Functions
| PIN | I/O(1) | DESCRIPTION | |||
|---|---|---|---|---|---|
| NUMBER | NAME | ||||
| 4–5 | BOOT | I | Input voltage supply of the high-side linear regulator. The external bootstrap capacitor is placed between BOOT and ASW. The cathode of the external bootstrap diode is connected to this pin. A Zener diode clamp may be needed between BOOT and ASW in order to not exceed the absolute maximum electrical rating. | ||
| 6, 9–12 | ASW | — | High-side driver signal return. ASW(6) is internally connected to PSW and the high-side thermal pad. Connect ASW(9-12) to ASW externally. | ||
| 13–14 | BST | O | For bootstrap charging that utilizes the internal bootstrap switch, this pin serves as the bootstrap diode anode connection point. The external high-side bootstrap capacitor can be charged through this pin using the input voltage applied to VIN, internal bootstrap switch, and external bootstrap diode(s). | ||
| 15 | BP7L | O | Low-side 7-V linear regulator output. A minimum of 1-uF capacitance is required from BP7L to AGND. | ||
| 16–17 | VIN | I | Gate driver input voltage supply. Input voltage range is from 10 V to 14 V. This pin serves as the input to the low-side linear regulators and the internal bootstrap switch. For bootstrap charging directly from the input voltage, VIN also serves as the bootstrap diode anode connection point. | ||
| 18, 24 | AGND | — | Low-side driver signal return. AGND(24) is internally connected to PGND and the low-side thermal pad. Connect AGND(18) to AGND externally. | ||
| 19 | DHL | I | High-side to low-side dead time set. In PWM mode, a resistor from DHL to AGND sets the dead time between the high-side turn-off and low-side turn-on. In independent input mode (IIM), DHL is used to configure the input interlock protection of the driver. DHL is connected to BP5L in IIM with interlock enabled. A resistor valued between 100 kΩ and 220 kΩ is connected from DHL to AGND for IIM with interlock disabled. | ||
| 20 | DLH | I | Low-side to high-side dead time set. In PWM mode, a resistor from DLH to AGND sets the dead time between the low-side turn-off and high-side turn-on. In independent input mode (IIM), DLH is used to configure the input interlock protection of the driver. A resistor valued between 100 kΩ and 220 kΩ is connected from DLH to AGND for IIM with interlock enabled. DLH is connected to BP5L in IIM with interlock disabled. | ||
| 21 | PGOOD | O | Power good pin. Asserts low when any of the low-side internal linear regulators or VIN goes into undervoltage lockout. Requires a 10-kΩ pull-up resistor to BP5L. | ||
| 22 | EN_HI | I | Enable input or high-side driver control input. In PWM mode this is used as an enable pin. In independent input mode (IIM) this serves as the control input for the high-side driver. | ||
| 23 | PWM_LI | I | PWM input or low-side driver control input. In PWM mode this is used as the PWM input to the gate driver. In independent input mode (IIM) this serves as the control input for the low-side driver. | ||
| 25–27 | PGND | — | Low-side power ground. Connect to the source of the low-side GaN FET. Internally connected to AGND and low-side thermal pad. Connect to AGND at printed circuit board level. | ||
| 28–30 | BP5L | O | Low-side 5-V linear regulator output. A minimum of 1-μF capacitance is required from BP5L to PGND. | ||
| 31–33 | LOH | O | Low-side driver source current ouput. Connect to the gate of low-side GaN FET with short, low inductance path. A resistor between LOH and the gate of the GaN FET can be used to adjust the turn-on speed. | ||
| 34–36 | LOL | O | Low-side driver sink current output. Connect to the gate of the low-side GaN FET with short, low inductance path. A resistor between LOL and the gate of the GaN FET can be used to adjust the turn-off speed. | ||
| 37–39 | PSW | — | Switch node connection. Connect to the source of the high-side GaN FET. Internally connected to ASW and high-side thermal pad. Connect to ASW at printed circuit board level. | ||
| 40–42 | BP5H | O | High-side 5-V linear regulator output. A minimum of 1-μF capacitance is required from BP5H to PSW. | ||
| 43–45 | HOH | O | High-side driver source current output. Connect to the gate of the high-side GaN FET with short, low inductance path. A resistor between HOH and the gate of the GaN FET can be used to adjust the turn-on speed. | ||
| 46–48 | HOL | O | High-side driver sink current output. Connect to the gate of the high-side GaN FET with short, low inductance path. A resistor between HOL and the gate of the GaN FET can be used to adjust the turn-off speed. | ||
| 1–3, 7–8 | NC | — | No connect. These pins are not connected internally. They can be left unconnected or connected to the high-side reference voltage (ASW) in order to avoid floating metal and prevent charge buildup. | ||
| — | PSW PAD | — | High-side thermal pad. Internally connected to ASW(6) and PSW. Connect to SW pins. | ||
| — | PGND PAD | — | Low-side thermal pad. Internally connected to AGND(18) and PGND. Connect to GND pins. | ||
(1) I = Input, O = Output, I/O =
Input or Output, — = Other
7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature (unless otherwise noted)(1)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VIN to AGND | –0.3 | 16 | V | |
| BP7L to AGND | –0.3 | 8 | V | |
| BP5L to AGND | –0.3 | 7 | V | |
| BP5H to SW | –0.3 | 7 | V | |
| BOOT to SW | –0.3 | VSW + 16 | V | |
| EN_HI | –0.3 | 16 | V | |
| PWM_LI | –0.3 | 16 | V | |
| DHL, DLH | –0.3 | VBP5L + 0.3 | V | |
| LOH, LOL | –0.3 | VBP5L + 0.3 | V | |
| HOH, HOL | VSW – 0.3 | VBP5H + 0.3 | V | |
| PGOOD | –0.3 | VBP5L + 0.3 | V | |
| SW to AGND (TPS7H6003-SP) | –10 | 200 | V | |
| SW to AGND (TPS7H6013-SP) | –10 | 60 | V | |
| SW to AGND (TPS7H6023-SP) | –10 | 22 | V | |
| BOOT to AGND (TPS7H6003-SP) | 0 | 216 | V | |
| BOOT to AGND (TPS7H6013-SP) | 0 | 76 | V | |
| BOOT to AGND (TPS7H6023-SP) | 0 | 38 | V | |
| BST to AGND | –0.3 | 16 | V | |
| BST current (3-µs transient pulse, non-repetitive) | 4 | A | ||
| Junction temperature, TJ | –55 | 150 | °C | |
| Storage temperature, Tstg | –65 | 150 | °C | |
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
| V(ESD) | Electrostatic discharge | Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) | ±500 | V |
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| VIN to AGND | 10 | 14 | V | |||
| EN_HI | 0 | 14 | V | |||
| PWM_LI | 0 | 14 | V | |||
| BOOT to SW | VSW + 8 | VSW + 14 | V | |||
| SW (TPS7H6003-SP) | –10 | 150 | V | |||
| SW (TPS7H6013-SP) | –10 | 45 | V | |||
| SW (TPS7H6023-SP) | –10 | 14 | V | |||
| SW slew rate | 100 | V/ns | ||||
| VIN slew rate | 0.03 | V/µs | ||||
| PWM_LI, EN_HI slew rate | 2 | V/µs | ||||
| Operating junction temperature | –55 | 125 | °C | |||
7.4 Thermal Information
| THERMAL METRIC(1) | TPS7H60x3-SP | UNIT | |
|---|---|---|---|
| CFP | |||
| 48 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 22.3 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 7.1 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 6.2 | °C/W |
| RθJB | Junction-to-board thermal resistance | 8.5 | °C/W |
| ΨθJT | Junction-to-top characterization parameter | 3.7 | °C/W |
| ΨθJB | Junction-to-board characterization parameter | 8.3 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.5 Electrical Characteristics
Specifications are over ambient temperature operating range TA = –55°C to 125°C, VIN = 10 V to 14 V, VBP5L = VBP5H = 5 V, and no load on LOH, LOL, HOH, and HOL (unless otherwise noted).
| PARAMETER | TEST CONDITIONS | SUBGROUP(1) | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|---|
| SUPPLY CURRENTS | ||||||||
| IQLS | Low-side quiescent current | VIN = 12 V, BOOT = 10 V |
MODE = PWM, EN = 0 V | 1, 2, 3 | 5 | 6.8 | mA | |
| MODE = IIM, LI = HI = 0 V |
1, 2, 3 | 5 | 8 | |||||
| IQHS | High-side quiescent current | VIN = 12 V, BOOT = 10 V |
MODE = PWM, EN = 0 V | 1, 2, 3 | 4 | 6.3 | mA | |
| MODE = IIM, LI = HI = 0 V |
1, 2, 3 | 4 | 6.3 | |||||
| IQBG | BOOT to AGND quiescent current (TPS7H6003-SP) | SW = 100 V, BOOT = 110 V | 20 | µA | ||||
| IQBG | BOOT to AGND quiescent current (TPS7H6013-SP) | SW = 28 V, BOOT = 38 V | 15 | µA | ||||
| IQBG | BOOT to AGND quiescent current (TPS7H6023-SP) | SW = 12 V, BOOT = 22 V | 10 | µA | ||||
| IOP_BG | BOOT to AGND operating current (TPS7H6003-SP) | SW = 100 V, BOOT = 110 V | 20 | µA | ||||
| IOP_BG | BOOT to AGND operating current (TPS7H6013-SP) | SW = 28 V, BOOT = 38 V | 15 | µA | ||||
| IOP_BG | BOOT to AGND operating current (TPS7H6023-SP) | SW = 12 V, BOOT = 22 V | 10 | µA | ||||
| IOP_LS | Low-side operating current | MODE = PWM, no load for LOL and LOH | f = 500 kHz | 1, 2, 3 | 6 | 9 | mA | |
| f = 1 MHz | 1, 2, 3 | 8 | 11 | |||||
| f = 2 MHz | 1, 2, 3 | 12 | 16 | |||||
| f = 5 MHz | 1, 2, 3 | 20 | 30 | |||||
| MODE = IIM, no load for LOL and LOH | f = 500 kHz | 1, 2, 3 | 6 | 9 | ||||
| f = 1 MHz | 1, 2, 3 | 8 | 12 | |||||
| f = 2 MHz | 1, 2, 3 | 11 | 17 | |||||
| f = 5 MHz | 1, 2, 3 | 20 | 30 | |||||
| IOP_HS | High-side operating current | MODE = PWM, no load for HOL and HOH | f = 500 kHz | 1, 2, 3 | 5 | 6.5 | mA | |
| f = 1 MHz | 1, 2, 3 | 5.3 | 8 | |||||
| f = 2 MHz | 1, 2, 3 | 7 | 10.5 | |||||
| f = 5 MHz | 1, 2, 3 | 13 | 17.5 | |||||
| MODE = IIM, no load for HOL and HOH | f = 500 kHz | 1, 2, 3 | 4.5 | 6.5 | ||||
| f = 1 MHz | 1, 2, 3 | 5.3 | 8 | |||||
| f = 2 MHz | 1, 2, 3 | 7 | 10.5 | |||||
| f = 5 MHz | 1, 2, 3 | 11.7 | 15 | |||||
| LOW-SIDE TO HIGH-SIDE CAPACITANCE | ||||||||
| Low-side to high-side capacitance | Low-side pins shorted together and high-side pins shorted together | 6 | pF | |||||
| GATE DRIVER | ||||||||
| VOL | Low-level output voltage | IOL = 100 mA | 1, 2, 3 | 0.07 | 0.15 | V | ||
| BP5x – VOH | High-level output voltage | IOH = 100 mA | 1, 2, 3 | 0.13 | 0.3 | V | ||
| IOH | Peak source current | HOH, LOH = 0 V, BP5x = 5 V | 1, 2, 3 | 0.7 | 1.3 | 2.3 | A | |
| IOL | Peak sink current | HOL, LOL = 5 V, BP5x = 5 V | 1, 2, 3 | 1.6 | 2.5 | 4.6 | A | |
| INTERNAL REGULATORS | ||||||||
| VBP5L | Low-side 5-V regulator output voltage | CBP5L = 1 µF | 1, 2, 3 | 4.75 | 5.0 | 5.175 | V | |
| Required BP5L output capacitor (2) | 1, 2, 3 | 1 | µF | |||||
| VBP5H | High-side 5-V regulator output voltage | CBP5H = 1 µF | 1, 2, 3 | 4.75 | 5.0 | 5.175 | V | |
| Required BP5H output capacitor (2) | 1 | µF | ||||||
| VBP7L | 7-V regulator output voltage | 1, 2, 3 | 6.65 | 7 | 7.35 | V | ||
| Required BP7L output capacitor (2) | 1 | µF | ||||||
| UNDERVOLTAGE PROTECTION | ||||||||
| BP5HR | BP5H UVLO rising threshold | CBP5H = 1 µF | 1, 2, 3 | 4.0 | 4.25 | 4.5 | V | |
| BP5HF | BP5H UVLO falling threshold | CBP5H = 1 µF | 1, 2, 3 | 3.8 | 4.05 | 4.3 | ||
| BP5HH | BP5H UVLO hysteresis | CBP5H = 1 µF | 0.2 | |||||
| BP5LR | BP5L UVLO rising threshold | CBP5L = 1 µF | 1, 2, 3 | 4.0 | 4.25 | 4.5 | V | |
| BP5LF | BP5L UVLO falling threshold | CBP5L = 1 µF | 1, 2, 3 | 3.8 | 4.05 | 4.3 | ||
| BP5LH | BP5L UVLO hysteresis | CBP5L = 1 µF | 0.2 | |||||
| BP7LR | BP7L UVLO rising threshold | CBP7L = 1 µF | 1, 2, 3 | 6.2 | 6.5 | 6.8 | V | |
| BP7LF | BP7L UVLO falling threshold | CBP7L = 1 µF | 1, 2, 3 | 5.9 | 6.2 | 6.5 | ||
| BP7LH | BP7L UVLO hysteresis | CBP7L = 1 µF | 0.3 | |||||
| VINR | VIN UVLO rising threshold | 1, 2, 3 | 8.0 | 8.6 | 9.0 | V | ||
| VINF | VIN UVLO falling threshold | 1, 2, 3 | 7.5 | 8.1 | 8.5 | |||
| VINH | VIN UVLO hysteresis | 0.53 | ||||||
| BOOTR | BOOT UVLO rising threshold | 1, 2, 3 | 6.6 | 7.1 | 7.4 | V | ||
| BOOTF | BOOT UVLO falling threshold | 1, 2, 3 | 6.2 | 6.65 | 7 | |||
| BOOTH | BOOT UVLO hysteresis | 0.45 | ||||||
| INPUT PINS | ||||||||
| VIR | Input rising edge threshold | 1, 2, 3 | 1.80 | 2.65 | V | |||
| VIF | Input falling edge threshold | 1, 2, 3 | 1.15 | 1.85 | V | |||
| VIHYS | Input hysteresis | 0.8 | V | |||||
| RPD | Input pull-down resistance | V = 2.15 V applied at input (EN_HI or PWM_LI) | 1, 2, 3 | 100 | 400 | kΩ | ||
| PROGRAMMBLE DEAD TIME | ||||||||
| TDLH | LO off to HO on dead time | MODE = PWM, LO falling to HO rising (90% to 10%), f ≤ 2 MHz | RLH = 3.32 kΩ |
9, 10 , 11 | 0 | 4.5 | 10 | ns |
| RLH = 11.8 kΩ | 9, 10 , 11 | 8 | 12 | 15.5 | ||||
| RLH = 21 kΩ | 9, 10 , 11 | 15.5 | 21 | 24 | ||||
| RLH = 52.3 kΩ | 9, 10 , 11 | 36 | 50 | 59 | ||||
| RLH = 105 kΩ | 9, 10 , 11 | 74 | 97 | 113.5 | ||||
| TDHL | HO off to LO on dead time | MODE = PWM, HO falling to LO rising (90% to 10%), f ≤ 2 MHz | RHL = 7.87 kΩ | 9, 10 , 11 | 0 | 5 | 10 | ns |
| RHL = 13.3 kΩ | 9, 10 , 11 | 6 | 10.5 | 15 | ||||
| RHL = 23.7 kΩ | 9, 10 , 11 | 16 | 21 | 24.5 | ||||
| RHL = 57.6 kΩ | 9, 10 , 11 | 44 | 53 | 61 | ||||
| RHL = 113 kΩ | 9, 10 , 11 | 86 | 105 | 125 | ||||
| BOOTSTRAP DIODE SWITCH | ||||||||
| RBST_SW | Bootstrap diode switch resistance | IBST_SW = 100 mA | 1, 2, 3 | 0.43 | Ω | |||
| Bootstrap diode switch parallel resistance | IBST_RP = 1 mA | 1, 2, 3 | 0.8 | 1 | 1.2 | kΩ | ||
| POWER GOOD | ||||||||
| Logic-low output | IFLT = 1 mA | 1, 2, 3 | 0.4 | V | ||||
| PGOOD internal resistance | BP5L = 5 V, BP7L = 7 V, VIN = 12 V | 1, 2, 3 | 0.7 | 1 | 1.9 | MΩ | ||
| Minimum BP5L voltage for valid PGOOD output | 1, 2, 3 | 2 | 2.45 | V | ||||
(1) Subgroups are applicable for QML parts. For subgroup definitions, see Quality Conformance Inspection.
(2) Specified by design; not tested in production.
7.6 Switching Characteristics
Specifications are over ambient temperature operating range TA = –55°C to 125°C, VIN = 10 V to 14 V, VBP5L = VBP5H = 5 V, and no load on LOH, LOL, HOH, and HOL (unless otherwise noted).
| PARAMETER | TEST CONDITIONS | SUBGROUP(1) | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|---|
| tLPHL | LO turnoff propagation delay | MODE = PWM | PWM rising to LOL falling | 9, 10, 11 | 30 | 48 | ns | |
| MODE = IIM | LI falling to LOL falling | 9, 10, 11 | 27 | 38 | ||||
| tLPLH | LO turnon propagation delay | MODE = IIM | LI rising to LOH rising | 9, 10, 11 | 24 | 38 | ns | |
| tHPHL | HO turnoff propagation delay | MODE = PWM | PWM falling to HOL falling | 9, 10, 11 | 35 | 50 | ns | |
| MODE = IIM | HI falling to HOL falling | 9, 10, 11 | 30 | 40 | ||||
| tHPLH | HO turnon propagation delay | MODE = IIM | HI rising to HOH rising | 9, 10, 11 | 26 | 40 | ns | |
| tMON | Delay matching LO on and HO off(3) | MODE = IIM | 9, 10, 11 | 5.5 | 12 | ns | ||
| tMOFF | Delay matching LO off and HO on(3) | MODE = IIM | 9, 10, 11 | 1.5 | 4 | ns | ||
| tHRC | HO rise time | CL = 1000 pF | 10% to 90% | 9, 10, 11 | 3.5 | 7.5 | ns | |
| tLRC | LO rise time | 9, 10, 11 | 3 | 7.5 | ||||
| tHFC | HO fall time | 90% to 10% | 9, 10, 11 | 4 | 5.5 | |||
| tLFC | LO fall time | 9, 10, 11 | 3 | 5.5 | ||||
| tPW_IIM | Minimum input pulse width (turn-on) | MODE = IIM | 9, 10, 11 | 5 | 8 | ns | ||
| tPW_IIM_OFF | Minimum input pulse width (turn-off) | MODE = IIM | 9, 10, 11 | 8 | 12 | ns | ||
| tPW_PWM | Minimum required input pulse width for targeted dead time (2) | MODE = PWM, RLH = 11.8 kΩ, RHL = 13.3 kΩ, DT reduction ≤ 2 ns |
22 | ns | ||||
| tPW_PWM | Minimum required input pulse width for targeted dead time (2) | MODE = PWM, RLH = 21 kΩ, RHL = 23.7 kΩ, DT reduction ≤ 3 ns |
30 | ns | ||||
(1) Subgroups are applicable for QML parts. For subgroup definitions, see the Quality Conformance Inspection table.
(2) Specified by design; not tested in production.
(3) Specification limits for this parameter are respresented as an absolute value.
7.7 Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
| SUBGROUP | DESCRIPTION | TEMP (°C) |
|---|---|---|
| 1 | Static tests at | 25 |
| 2 | Static tests at | 125 |
| 3 | Static tests at | –55 |
| 4 | Dynamic tests at | 25 |
| 5 | Dynamic tests at | 125 |
| 6 | Dynamic tests at | –55 |
| 7 | Functional tests at | 25 |
| 8A | Functional tests at | 125 |
| 8B | Functional tests at | –55 |
| 9 | Switching tests at | 25 |
| 10 | Switching tests at | 125 |
| 11 | Switching tests at | –55 |
7.8 Typical Characteristics
Figure 7-1 BP5L Output Voltage vs VIN Voltage 
Figure 7-3 LO Turnoff Propagation Delay vs VIN
Voltage (PWM)
Figure 7-5 LO Turnon Propagation Delay vs VIN
Voltage (IIM)
Figure 7-7 HO Turnoff Propagation Delay vs VIN
Voltage (IIM)
Figure 7-9 Peak Source Current vs VIN
Voltage
| VIN = 12 V |
Figure 7-13 LO Output Rise Time vs VIN Voltage
Figure 7-15 BP7L Output Voltage vs VIN Voltage
Figure 7-17 Input Falling Edge Threshold vs VIN Voltage
Figure 7-19 LO off and HO on Delay Matching vs VIN Voltage
Figure 7-21 BP5L UVLO Falling Threshold vs VIN Voltage
Figure 7-23 BP5H UVLO Falling Threshold vs BOOT
Voltage
Figure 7-25 BP7L UVLO Falling Threshold vs VIN Voltage
Figure 7-27 VIN UVLO Falling Threshold vs Temperature
Figure 7-29 BOOT UVLO Falling Threshold vs Temperature
| RLH = 11.8 kΩ |
| RLH = 52.3 kΩ |
| RHL = 7.87 kΩ |
| RHL = 23.7 kΩ |
| RHL = 113 kΩ |
Figure 7-41 High-Side Quiescent Current vs BOOT Voltage
| VIN = 12 V |
| VBOOT = 10 V |
Figure 7-2 BP5H Output Voltage vs BOOT
Voltage
Figure 7-4 LO Turnoff Propagation Delay vs VIN
Voltage (IIM)
Figure 7-6 HO Turnoff Propagation Delay vs VIN
Voltage (PWM)
Figure 7-8 HO Turnon Propagation Delay vs VIN
Voltage (IIM)
Figure 7-10 Peak Sink Current vs VIN
Voltage
| VIN = 12 V |
Figure 7-14 HO Output Rise Time vs BOOT Voltage
Figure 7-16 Input Rising Edge Threshold vs VIN Voltage
Figure 7-18 LO on and HO off Delay Matching vs VIN Voltage
Figure 7-20 BP5L UVLO Rising Threshold vs VIN Voltage
Figure 7-22 BP5H UVLO Rising Threshold vs BOOT Voltage
Figure 7-24 BP7L UVLO Rising Threshold vs VIN
Voltage
Figure 7-26 VIN UVLO Rising Threshold vs Temperature
Figure 7-28 BOOT UVLO Rising Threshold vs Temperature
| RLH = 3.32 kΩ |
| RLH = 21 kΩ |
| RLH = 105 kΩ |
| RHL = 13.3 kΩ |
| RHL = 57.6 kΩ |
Figure 7-40 Low-Side Quiescent Current vs VIN Voltage
| VIN = 12 V |
| VBOOT = 10 V |
8 Detailed Description
8.1 Overview
The TPS7H60x3-SP series of radiation-hardness-assured (RHA) half-bridge gate drivers are intended for use with enhancement mode GaN FETs. The series consists of the TPS7H6003-SP (200-V driver), TPS7H6013-SP (60-V driver), and the TPS7H6023-SP (22-V driver). The drivers can be utilized in high frequency, high efficiency GaN based power converter designs. Each driver is designed to have a propagation delay of 30 ns (typical) as well as 5.5 ns (typical) high-side to low-side delay matching.
The drivers contain high-side and low-side internal linear regulators. These ensure that the gate voltages are maintained at 5 V in order to prevent any damage of the GaN devices that are being driven. Split outputs on the high-side and low-side drivers provide the user the flexibility to independently adjust the turn-on and turn-off times of the GaN FETs. An external bootstrap diode is required for the gate drivers and as such, the user has the ability to optimize the diode based on the application. The drivers contain an internal switch in series with the bootstrap diode that can be used to prevent overcharging of the bootstrap capacitor and decreases reverse recovery losses in the diode.
The gate drivers have two modes of operation: PWM mode and independent input mode (IIM). The dual mode operation allows for each gate driver to be used with a wide number of PWM controllers to enable both synchronous rectifier control and GaN FET compatibility. The user also has the option to enable input interlock protection in IIM, allowing for anti-shoot through protection in synchronous buck and half-bridge topologies. This protection can also be disabled in IIM if desired, which allows the drivers to be utilized in two-switch forward converters and dual single ended applications.
