ZHCSOJ3C March   2023  – April 2025 ADC12DJ5200SE

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Comparison
      2. 6.3.2  Analog Inputs
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
      3. 6.3.3  ADC Core
        1. 6.3.3.1 ADC Theory of Operation
        2. 6.3.3.2 ADC Core Calibration
        3. 6.3.3.3 Analog Reference Voltage
        4. 6.3.3.4 ADC Overrange Detection
        5. 6.3.3.5 Code Error Rate (CER)
      4. 6.3.4  Temperature Monitoring Diode
      5. 6.3.5  Timestamp
      6. 6.3.6  Clocking
        1. 6.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.6.3.2 Automatic SYSREF Calibration
      7. 6.3.7  Programmable FIR Filter (PFIR)
        1. 6.3.7.1 Dual Channel Equalization
        2. 6.3.7.2 Single Channel Equalization
        3. 6.3.7.3 Time Varying Filter
      8. 6.3.8  Digital Down Converters (DDC)
        1. 6.3.8.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 6.3.8.1.1 NCO Fast Frequency Hopping (FFH)
          2. 6.3.8.1.2 NCO Selection
          3. 6.3.8.1.3 Basic NCO Frequency Setting Mode
          4. 6.3.8.1.4 Rational NCO Frequency Setting Mode
          5. 6.3.8.1.5 NCO Phase Offset Setting
          6. 6.3.8.1.6 52
          7. 6.3.8.1.7 NCO Phase Synchronization
        2. 6.3.8.2 Decimation Filters
        3. 6.3.8.3 Output Data Format
        4. 6.3.8.4 Decimation Settings
          1. 6.3.8.4.1 Decimation Factor
          2. 6.3.8.4.2 DDC Gain Boost
      9. 6.3.9  JESD204C Interface
        1. 6.3.9.1 Transport Layer
        2. 6.3.9.2 Scrambler
        3. 6.3.9.3 Link Layer
        4. 6.3.9.4 8B/10B Link Layer
          1. 6.3.9.4.1 Data Encoding (8B/10B)
          2. 6.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.9.4.3 Code Group Synchronization (CGS)
          4. 6.3.9.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.9.4.5 Frame and Multiframe Monitoring
        5. 6.3.9.5 64B/66B Link Layer
          1. 6.3.9.5.1 64B/66B Encoding
          2. 6.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 6.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 6.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 6.3.9.5.3.2 Forward Error Correction (FEC) Mode
          4. 6.3.9.5.4 Initial Lane Alignment
          5. 6.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.9.6 Physical Layer
          1. 6.3.9.6.1 SerDes Pre-Emphasis
        7. 6.3.9.7 JESD204C Enable
        8. 6.3.9.8 Multi-Device Synchronization and Deterministic Latency
        9. 6.3.9.9 Operation in Subclass 0 Systems
      10. 6.3.10 Alarm Monitoring
        1. 6.3.10.1 NCO Upset Detection
        2. 6.3.10.2 Clock Upset Detection
        3. 6.3.10.3 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode
      2. 6.4.2 Single-Channel Mode (DES Mode)
      3. 6.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 6.4.4 JESD204C Modes
        1. 6.4.4.1 JESD204C Operating Modes Table
        2. 6.4.4.2 JESD204C Modes cont.
        3. 6.4.4.3 JESD204C Transport Layer Data Formats
        4. 6.4.4.4 64B/66B Sync Header Stream Configuration
        5. 6.4.4.5 Dual DDC and Redundant Data Mode
      5. 6.4.5 Power-Down Modes
      6. 6.4.6 Test Modes
        1. 6.4.6.1 Serializer Test-Mode Details
        2. 6.4.6.2 PRBS Test Modes
        3. 6.4.6.3 Clock Pattern Mode
        4. 6.4.6.4 Ramp Test Mode
        5. 6.4.6.5 Short and Long Transport Test Mode
          1. 6.4.6.5.1 Short Transport Test Pattern
          2. 6.4.6.5.2 Long Transport Test Pattern
        6. 6.4.6.6 D21.5 Test Mode
        7. 6.4.6.7 K28.5 Test Mode
        8. 6.4.6.8 Repeated ILA Test Mode
        9. 6.4.6.9 Modified RPAT Test Mode
      7. 6.4.7 Calibration Modes and Trimming
        1. 6.4.7.1 Foreground Calibration Mode
        2. 6.4.7.2 Background Calibration Mode
        3. 6.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 6.4.8 Offset Calibration
      9. 6.4.9 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 Streaming Mode
    6. 6.6 SPI Register Map
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Wideband RF Sampling Receiver
        1. 7.2.1.1 Design Requirements
          1. 7.2.1.1.1 Input Signal Path
          2. 7.2.1.1.2 Clocking
        2. 7.2.1.2 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.8 Electrical Characteristics: AC Specifications (Single-Channel Mode)

typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, input signal applied to INA, fIN = 2347 MHz, AIN = –1 dBFS, fCLK = 5.12 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BW-1dB Input bandwidth -1dB range Low frequency 3.0 GHz
High frequency 5.8 GHz
BW-3dB Input bandwidth -3dB range Low frequency 2.0 GHz
High frequency 6.3 GHz
PFS Fullscale Input Power fIN = 4.5GHz, FS_RANGE_A = 0xA000 -1.25 dBm
CER Code error rate Maximum CER, does not include JESD204C interface BER 10–18 Errors/ sample
NOISEDC DC input noise standard deviation No input, foreground calibration, excludes DC offset, includes fixed interleaving spurs (fS / 2 and fS / 4 spurs), OS_CAL enabled 2.8 LSB
NSD Noise spectral density, excludes fixed interleaving spurs (fS / 2 and fS / 4 spur) Maximum full-scale voltage (FS_RANGE_A = 0xFFFF), AIN = –20 dBFS –153.1 dBFS/
Hz
Default full-scale voltage (FS_RANGE_A = 0xA000), AIN = –20 dBFS –151.5
NF Noise figure, ZS = 50 Ω Maximum full-scale voltage (FS_RANGE_A = 0xFFFF), AIN = –20 dBFS 20.9 dB
Default full-scale voltage (FS_RANGE_A = 0xA000), AIN = –20 dBFS 22.5
SNR Signal-to-noise ratio, excluding DC, HD2 to HD9, fS / 2, fS / 4, fS / 2 – fIN, fS / 4 ± fIN fIN = 2397 MHz AIN = –1 dBFS 50 53.5 dBFS
AIN = –3 dBFS 54
AIN = –12 dBFS 54.7
AIN = –3 dBFS, FS_RANGE_A = 0xFFFF 55.1
fIN = 4197 MHz AIN = –1 dBFS 52.1
AIN = –3 dBFS 53.0
AIN = –12 dBFS 54.6
fIN = 5997 MHz AIN = –1 dBFS 50.6
AIN = –3 dBFS 51.8
AIN = –12 dBFS 54.4
SINAD Signal-to-noise and distortion ratio, excluding DC and fS / 2 fixed spurs fIN = 2397 MHz AIN = –1 dBFS 50.7 dBFS
AIN = –3 dBFS 52.0
AIN = –12 dBFS 54.1
AIN = –3 dBFS, FS_RANGE_A = 0xFFFF 52.6
fIN = 4197 MHz AIN = –1 dBFS 49.0
AIN = –3 dBFS 50.8
AIN = –12 dBFS 54.7
fIN = 5997 MHz AIN = –1 dBFS 47.2
AIN = –3 dBFS 49.6
AIN = –12 dBFS 53.6
ENOB Effective number of bits, excluding DC and fS / 2 fixed spurs fIN = 2397 MHz AIN = –1 dBFS 8.2 bits
AIN = –3 dBFS 8.3
AIN = –12 dBFS 8.7
AIN = –3 dBFS, FS_RANGE_A = 0xFFFF 8.5
fIN = 4197 MHz AIN = –1 dBFS 7.9
AIN = –3 dBFS 8.2
AIN = –12 dBFS 8.6
fIN = 5997 MHz AIN = –1 dBFS 7.6
AIN = –3 dBFS 8.0
AIN = –12 dBFS 8.6
SFDR Spurious free dynamic range, excluding DC, fS / 4 and fS / 2 fixed spurs fIN = 2397 MHz AIN = –1 dBFS 56 dBFS
AIN = –3 dBFS 59
AIN = –12 dBFS 68
AIN = –3 dBFS, FS_RANGE_A = 0xFFFF 59
fIN = 4197 MHz AIN = –1 dBFS 54
AIN = –3 dBFS 57
AIN = –12 dBFS 66
fIN = 5997 MHz AIN = –1 dBFS 53
AIN = –3 dBFS 57
AIN = –12 dBFS 66
HD2 2nd-order harmonic distortion fIN = 2397 MHz AIN = –1 dBFS –66 -59 dBFS
AIN = –3 dBFS –73
AIN = –12 dBFS –84
AIN = –3 dBFS, FS_RANGE_A = 0xFFFF –69
fIN = 4197 MHz AIN = –1 dBFS –71
AIN = –3 dBFS –75
AIN = –12 dBFS –84
fIN = 5997 MHz AIN = –1 dBFS –66
AIN = –3 dBFS –70
AIN = –12 dBFS –83
HD3 3rd-order harmonic distortion fIN = 2397 MHz AIN = –1 dBFS –72 -58 dBFS
AIN = –3 dBFS –77
AIN = –12 dBFS –88
AIN = –3 dBFS, FS_RANGE_A = 0xFFFF –75
fIN = 4197 MHz AIN = –1 dBFS –62
AIN = –3 dBFS –68
AIN = –12 dBFS –78
fIN = 5997 MHz AIN = –1 dBFS –54
AIN = –3 dBFS –63
AIN = –12 dBFS –80
fS / 2 – fIN fS / 2 – fIN input signal dependent interleaving spur fIN = 2397 MHz AIN = –1 dBFS –58 dBFS
AIN = –3 dBFS –59
AIN = –12 dBFS –69
AIN = –3 dBFS, FS_RANGE_A = 0xFFFF –59
fIN = 4197 MHz AIN = –1 dBFS –55
AIN = –3 dBFS –58
AIN = –12 dBFS –66
fIN = 5997 MHz AIN = –1 dBFS –55
AIN = –3 dBFS –57
AIN = –12 dBFS –68
fS / 4 ± fIN fS / 4 ± fIN input signal dependent interleaving spur fIN = 2397 MHz AIN = –1 dBFS –66 -54 dBFS
AIN = –3 dBFS –67
AIN = –12 dBFS –77
AIN = –3 dBFS, FS_RANGE_A = 0xFFFF –68
fIN = 4197 MHz AIN = –1 dBFS –64
AIN = –3 dBFS –65
AIN = –12 dBFS –77
fIN = 5997 MHz AIN = –1 dBFS –62
AIN = –3 dBFS –64
AIN = –12 dBFS –72
fS / 2 fS / 2 fixed interleaving spur, independent of input signal AIN = –20 dBFS, OS_CAL disabled –55 dBFS
AIN = –20 dBFS, OS_CAL enabled –73
fS / 4 fS / 4 fixed interleaving spur, independent of input signal AIN = –20 dBFS –69 -55 dBFS
SPUR Worst spur, excluding DC, HD2, HD3, fS / 2, fS / 4, fS / 2 - fIN, and fS / 4 ± fIN fIN = 2397 MHz AIN = –1 dBFS –74 -62 dBFS
AIN = –3 dBFS –75
AIN = –12 dBFS –77
AIN = –3 dBFS, FS_RANGE_A = 0xFFFF –75
fIN = 4197 MHz AIN = –1 dBFS –68
AIN = –3 dBFS –71
AIN = –12 dBFS –73
fIN = 5997 MHz AIN = –1 dBFS –67
AIN = –3 dBFS –74
AIN = –12 dBFS –76
IMD3 3rd-order intermodulation distortion f1 = 2393 MHz,
f2 = 2403 MHz		 AIN = –7 dBFS per tone –73 dBFS
AIN = –9 dBFS per tone –78 dBFS
AIN = –18 dBFS per tone –92 dBFS
AIN = –9 dBFS per tone, FS_RANGE_A = 0xFFFF –75 dBFS
f1 = 4193 MHz,
f2 = 4203 MHz		 AIN = –7 dBFS per tone –70 dBFS
AIN = –9 dBFS per tone –77
AIN = –18 dBFS per tone –81
f1 = 5993 MHz,
f2 = 6003 MHz		 AIN = –7 dBFS per tone –57
AIN = –9 dBFS per tone –64
AIN = –18 dBFS per tone –84