ZHCSNM5C november   2020  – august 2023 UCC25800-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Oscillator
      3. 8.3.3 External Synchronization
      4. 8.3.4 Dead-Time
        1. 8.3.4.1 Adaptive Dead-time
        2. 8.3.4.2 Maximum Programmable Dead-time
      5. 8.3.5 Protections
        1. 8.3.5.1 Overcurrent Protection
          1. 8.3.5.1.1 OCP Threshold Setting
          2. 8.3.5.1.2 Output Power Capability
        2. 8.3.5.2 Input Overvoltage Protection (OVP)
        3. 8.3.5.3 Over-Temperature Protection (TSD)
        4. 8.3.5.4 Pin-Fault Protections
        5. 8.3.5.5 VREG Pin Protection
      6. 8.3.6 DIS/FLT Pin operation
        1. 8.3.6.1 FAULT Codes
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Soft-start Mode
      3. 8.4.3 Normal Operation Mode
      4. 8.4.4 Disabled Mode
      5. 8.4.5 Fault Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 LLC Converter Operation Principle
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

DIS/FLT Pin operation

The DIS/FLT pin is an input/output pin. It can be

  • Externally driven to enable or disable the transformer driver
  • Read as a status flag telling whether the transformer driver is in fault mode or not and specifically what fault it is
  • Left floating to enable the transformer driver by default

Internally the pin is tied high through a 100-kΩ pullup resistor from VREG. This pullup resistor activates only after the VREG pin is high. If the UCC25800-Q1 transformer driver enters the fault mode, the DIS/FLT pin is pulled low internally via a 750-µA current source. When the pin is low, switching is inhibited.

The DIS/FLT internal pulldown current source is activated during the power-up sequence once the VCC voltage exceeds the UVLO rising threshold. After the VREG voltage has risen above the VREGOK threshold, the pulldown current source is released and the DIS/FLT pin rises (unless it is externally pulled down). When the DIS/FLT pin voltage exceeds the ENTH threshold, the transformer driver is enabled. When DIS/FLT pin falls below the DISTH the transformer driver is disabled. When the transformer driver is disabled its power consumption is reduced to IVCCDIS.

If there is concern about noise coupling to the DIS/FLT pin it can be pulled up with an external resistor to an external rail or to VREG. In order to read the pin as a status flag, the external resistor value must be high enough that the 750-µA current source can pull the pin below the threshold level of the device reading the pin. It is recommended that the value for an external pullup resistor to 5 V is 10 kΩ and the value for an external pullup resistor to 3.3 V is 4.7 kΩ in order for the pin to be read as a fault output.

GUID-20211103-SS0I-SS2S-FCFV-XSQZXLCCKXWX-low.svgFigure 8-16 External Pullup for 3.3-V Supply
GUID-20211103-SS0I-V7DJ-WSKG-NKXCK91343KP-low.svgFigure 8-17 External Pullup for 5-V Supply

If the DIS/FLT pin functionality is not required, it can be left floating or tied to VREG to allow the transformer driver to operate normally.