PCMD3140 是一款高性能脉冲密度调制 (PDM) 输入至时分多路复用 (TDM) 或 I2S 输出转换器,最多可支持对 PDM 麦克风输入的四个数字通道进行同步采样。该器件集成了可编程数字音量控制、麦克风偏置电压、锁相环 (PLL)、可编程高通滤波器 (HPF)、双二阶滤波器、低延迟滤波器模式,并可实现高达 768 kHz 的输出采样率。该器件支持时分多路复用 (TDM)、I2S 或左平衡 (LJ) 音频格式,并可通过 I2C 接口进行控制。此外,PCMD3140 还支持主从模式选择,从而实现音频总线接口操作。这些集成的高性能特性,以及采用 3.3V 或 1.8V 单电源供电的功能,使该器件非常适用于远场麦克风录音应用中空间受限的音频系统。
PCMD3140 的额定工作温度范围为 –40°C 至 +125°C,并且采用 20 引脚 WQFN 封装。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
PCMD3140 | WQFN (20) | 3.00mm × 3.00mm,间距为 0.5mm |
Changes from Revision * (December 2020) to Revision A (June 2021)
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | NC | No connect | No connection |
2 | NC | No connect | No connection |
3 | PDMDIN1_GPI1 | Digital input | Digital input 1 (multipurpose functions such as digital microphones data, PLL input clock source, and so forth). |
4 | PDMCLK_GPO1 | Digital output | General-purpose digital output 1 (multipurpose functions such as digital microphone clock, interrupt, and so forth). |
5 | VSS | Ground supply | Device ground internally shorted to thermal pad. Short this package corner pin directly to the board ground plane. See the package drawing at the end of this document for corner pin dimensions. |
6 | SDOUT | Digital output | Audio serial data interface bus output. |
7 | BCLK | Digital I/O | Audio serial data interface bus bit clock. |
8 | FSYNC | Digital I/O | Audio serial data interface bus frame synchronization signal. |
9 | IOVDD | Digital supply | Digital I/O power supply (1.8 V or 3.3 V, nominal). |
10 | VSS | Ground supply | Device ground internally shorted to thermal pad. Short this package corner pin directly to the board ground plane. See the package drawing at the end of this document for corner pin dimensions. |
11 | GPIO1 | Digital I/O | General-purpose digital input/output 1 (multipurpose functions such as digital microphones clock or data, PLL input clock source, interrupt, and so forth). |
12 | SDA | Digital I/O | Data pin for I2C control bus. |
13 | SCL | Digital input | Clock pin for I2C control bus. |
14 | DREG | Digital supply | Digital regulator output voltage for digital core supply (1.5 V, nominal). Connect a 10-µF and a 0.1-µF low ESR capacitor in parallel to the device ground (VSS). |
15 | VSS | Ground supply | Device ground internally shorted to thermal pad. Short this package corner pin directly to the board ground plane. See the package drawing at the end of this document for corner pin dimensions. |
16 | AVDD | Analog supply | Analog power (1.8 V or 3.3 V, nominal). |
17 | AREG | Analog supply | Analog on-chip regulator output voltage for analog supply (1.8 V, nominal) or external analog power (1.8 V, nominal). Connect a 10-µF and a 0.1-µF low ESR capacitor in parallel to the analog ground (AVSS). |
18 | VREF | Analog | Analog reference voltage filter output. Connect a 1-µF to the analog ground (AVSS). |
19 | PDMDIN2_GPI2 | Analog output/digital input | Digital Input 2. MICBIAS output or general-purpose digital input 2 (multipurpose functions such as digital microphones data, MICBIAS, PLL input clock source, and so forth). If used as MICBIAS output, then connect a 1 µF to analog ground (AVSS) |
20 | VSS | Ground supply | Device ground internally shorted to thermal pad. Short this package corner pin directly to the board ground plane. See the package drawing at the end of this document for corner pin dimensions. |
Thermal Pad | Thermal Pad (VSS) | Ground supply | Thermal pad is shorted to the internal device ground. Short the thermal pad directly to the board ground plane. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | AVDD to AVSS | –0.3 | 3.9 | V |
AREG to AVSS | –0.3 | 2.0 | ||
IOVDD to VSS (thermal pad) | –0.3 | 3.9 | ||
Ground voltage differences | AVSS to VSS (thermal pad) | –0.3 | 0.3 | V |
Digital input voltage | Digital input except PDMDINx_GPIx pins voltage to VSS (thermal pad) | –0.3 | IOVDD + 0.3 | V |
Digital input PDMDINx_GPIx pins voltage to VSS (thermal pad) | –0.3 | AVDD + 0.3 | ||
Temperature | Operating ambient, TA | –40 | 125 | °C |
Junction, TJ | –40 | 150 | ||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V | |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
POWER | ||||||
AVDD, AREG(1) | Analog supply voltage AVDD to AVSS (AREG is generated using onchip regulator) - AVDD 3.3-V operation | 3.0 | 3.3 | 3.6 | V | |
Analog supply voltage AVDD and AREG to AVSS (AREG internal regulator is shutdown) - AVDD 1.8-V operation | 1.7 | 1.8 | 1.9 | |||
IOVDD | IO supply voltage to VSS (thermal pad) - IOVDD 3.3-V operation | 3.0 | 3.3 | 3.6 | V | |
IO supply voltage to VSS (thermal pad) - IOVDD 1.8-V operation | 1.65 | 1.8 | 1.95 | |||
INPUTS | ||||||
Digital input except PDMDIN1_GPI1 and PDMDIN2_GPI2 pins voltage to VSS (thermal pad) | 0 | IOVDD | V | |||
Digital input PDMDIN1_GPI1 and PDMDIN2_GPI2 pins voltage to VSS (thermal pad) | 0 | AVDD | V | |||
TEMPERATURE | ||||||
TA | Operating ambient temperature | –40 | 125 | °C | ||
OTHERS | ||||||
GPIOx or GPIx (used as MCLK input) clock frequency | 36.864 | MHz | ||||
Cb | SCL and SDA bus capacitance for I2C interface supports standard-mode and fast-mode | 400 | pF | |||
SCL and SDA bus capacitance for I2C interface supports fast-mode plus | 550 | |||||
CL | Digital output load capacitance | 20 | 50 | pF |
THERMAL METRIC(1) | PCMD3140 | UNIT | |
---|---|---|---|
RTW (WQFN) | |||
24 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 55.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 33.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 23.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 23.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 16.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
PERFORMANCE FOR PDM INPUT CONVERSION | |||||||
SNR | Signal-to-noise ratio, A-weighted(1) (2) (3) | No signal, input generated using 5th-order PDM modulator | 130 | dB | |||
No signal, input generated using 4th-order PDM modulator | 118 | ||||||
DR | Dynamic range, A-weighted(2) (3) | –60-dB full-scale signal input, input generated using 5th-order PDM modulator | 127 | dB | |||
–60-dB full-scale signal input, input generated using 4th-order PDM modulator | 116 | ||||||
OTHER PARAMETERS | |||||||
Digital volume control range | Programmable 0.5-dB steps | –100 | 27 | dB | |||
Output data sample rate | Programmable | 7.35 | 768 | kHz | |||
Output data sample word length | Programmable | 16 | 32 | Bits | |||
Digital high-pass filter cutoff frequency | First-order IIR filter with programmable coefficients, –3-dB point (default setting) |
12 | Hz | ||||
MICROPHONE BIAS | |||||||
MICBIAS noise | BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor between MICBIAS and AVSS | 2.1 | µVRMS | ||||
MICBIAS voltage | MICBIAS programmed to VREF and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V | VREF | V | ||||
MICBIAS voltage | MICBIAS programmed to VREF × 1.096 and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V | VREF × 1.096 | V | ||||
MICBIAS voltage | Bypass to AVDD with 5-mA load | AVDD – 0.2 | V | ||||
MICBIAS current drive | 5 | mA | |||||
MICBIAS load regulation | MICBIAS programmed to either VREF or VREF × 1.096, measured up to max load | 0 | 0.6 | 1 | % | ||
MICBIAS overcurrent protection threshold | 6.1 | mA | |||||
DIGITAL I/O | |||||||
VIL | Low-level digital input logic voltage threshold | All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2, SDA and SCL, IOVDD 1.8-V operation | –0.3 | 0.35 × IOVDD | V | ||
All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2, SDA and SCL, IOVDD 3.3-V operation | –0.3 | 0.8 | |||||
VIH | High-level digital input logic voltage threshold | All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2, SDA and SCL, IOVDD 1.8-V operation | 0.65 × IOVDD | IOVDD + 0.3 | V | ||
All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2, SDA and SCL, IOVDD 3.3-V operation | 2 | IOVDD + 0.3 | |||||
VOL | Low-level digital output voltage | All digital pins except PDMCLK_GPO1, SDA and SCL, IOL = –2 mA, IOVDD 1.8-V operation |
0.45 | V | |||
All digital pins except PDMCLK_GPO1, SDA and SCL, IOL = –2 mA, IOVDD 3.3-V operation |
0.4 | ||||||
VOH | High-level digital output voltage | All digital pins except PDMCLK_GPO1, SDA and SCL, IOH = 2 mA, IOVDD 1.8-V operation |
IOVDD – 0.45 | V | |||
All digital pins except PDMCLK_GPO1, SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation |
2.4 | ||||||
VIL(I2C) | Low-level digital input logic voltage threshold | SDA and SCL | –0.5 | 0.3 x IOVDD | V | ||
VIH(I2C) | High-level digital input logic voltage threshold | SDA and SCL | 0.7 x IOVDD | IOVDD + 0.5 | V | ||
VOL1(I2C) | Low-level digital output voltage | SDA, IOL(I2C) = –3 mA, IOVDD > 2 V | 0.4 | V | |||
VOL2(I2C) | Low-level digital output voltage | SDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V | 0.2 x IOVDD | V | |||
IOL(I2C) | Low-level digital output current | SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode | 3 | mA | |||
SDA, VOL(I2C) = 0.4 V, fast-mode plus | 20 | ||||||
IIH | Input logic-high leakage for digital inputs | All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2 pins, input = IOVDD |
–5 | 0.1 | 5 | µA | |
IIL | Input logic-low leakage for digital inputs | All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2 pins, input = 0 V |
–5 | 0.1 | 5 | µA | |
VIL(GPIx) | Low-level digital input logic voltage threshold | PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD 1.8-V operation | –0.3 | 0.35 × AVDD | V | ||
PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD 3.3-V operation | –0.3 | 0.8 | |||||
VIH(GPIx) | High-level digital input logic voltage threshold | PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD 1.8-V operation | 0.65 × AVDD | AVDD + 0.3 | V | ||
PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD 3.3-V operation | 2 | AVDD + 0.3 | |||||
VOL(GPOx) | Low-level digital output voltage | PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, IOL = –2 mA, AVDD 1.8-V operation | 0.45 | V | |||
PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, IOL = –2 mA, AVDD 3.3-V operation | 0.4 | ||||||
VOH(GPOx) | High-level digital output voltage | PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, IOH = 2 mA, AVDD 1.8-V operation | AVDD – 0.45 | V | |||
PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, IOH = 2 mA, AVDD 3.3-V operation | 2.4 | ||||||
IIH(GPIx) | Input logic-high leakage for digital inputs | PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, input = AVDD | –5 | 0.1 | 5 | µA | |
IIL(GPIx) | Input logic-high leakage for digital inputs | PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, input = 0 V | –5 | 0.1 | 5 | µA | |
CIN | Input capacitance for digital inputs | All digital pins | 5 | pF | |||
RPD | Pulldown resistance for digital I/O pins when asserted on | 20 | kΩ | ||||
TYPICAL SUPPLY CURRENT CONSUMPTION | |||||||
IAVDD | Current consumption in sleep mode (software shutdown mode) | All external clocks stopped, AVDD = 3.3 V | 5 | µA | |||
IAVDD | All external clocks stopped, AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) | 10 | |||||
IIOVDD | All external clocks stopped, IOVDD = 3.3 V | 0.5 | |||||
IIOVDD | All external clocks stopped, IOVDD = 1.8 V | 0.3 | |||||
IAVDD | Current consumption with 4-channel PDM input recording | AVDD = 3.3 V | 9.1 | mA | |||
IAVDD | AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) | 8.1 | |||||
IIOVDD | IOVDD = 3.3 V | 0.1 | |||||
IIOVDD | IOVDD = 1.8 V | 0.05 | |||||
IAVDD | Current consumption with 4-channel PDM input recording, fS = 16 kHz, PDMCLKx = 96 × fS, PLL off and BCLK = 384 × fS | AVDD = 3.3 V | 7.3 | mA | |||
IAVDD | AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) | 6.3 | |||||
IIOVDD | IOVDD = 3.3 V | 0.1 | |||||
IIOVDD | IOVDD = 1.8 V | 0.05 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
STANDARD-MODE | |||||
fSCL | SCL clock frequency | 0 | 100 | kHz | |
tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated. | 4 | μs | ||
tLOW | Low period of the SCL clock | 4.7 | μs | ||
tHIGH | High period of the SCL clock | 4 | μs | ||
tSU;STA | Setup time for a repeated START condition | 4.7 | μs | ||
tHD;DAT | Data hold time | 0 | 3.45 | μs | |
tSU;DAT | Data setup time | 250 | ns | ||
tr | SDA and SCL rise time | 1000 | ns | ||
tf | SDA and SCL fall time | 300 | ns | ||
tSU;STO | Setup time for STOP condition | 4 | μs | ||
tBUF | Bus free time between a STOP and START condition | 4.7 | μs | ||
FAST-MODE | |||||
fSCL | SCL clock frequency | 0 | 400 | kHz | |
tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated. | 0.6 | μs | ||
tLOW | Low period of the SCL clock | 1.3 | μs | ||
tHIGH | High period of the SCL clock | 0.6 | μs | ||
tSU;STA | Setup time for a repeated START condition | 0.6 | μs | ||
tHD;DAT | Data hold time | 0 | 0.9 | μs | |
tSU;DAT | Data setup time | 100 | ns | ||
tr | SDA and SCL rise time | 20 | 300 | ns | |
tf | SDA and SCL fall time | 20 × (IOVDD / 5.5 V) | 300 | ns | |
tSU;STO | Setup time for STOP condition | 0.6 | μs | ||
tBUF | Bus free time between a STOP and START condition | 1.3 | μs | ||
FAST-MODE PLUS | |||||
fSCL | SCL clock frequency | 0 | 1000 | kHz | |
tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated. | 0.26 | μs | ||
tLOW | Low period of the SCL clock | 0.5 | μs | ||
tHIGH | High period of the SCL clock | 0.26 | μs | ||
tSU;STA | Setup time for a repeated START condition | 0.26 | μs | ||
tHD;DAT | Data hold time | 0 | μs | ||
tSU;DAT | Data setup time | 50 | ns | ||
tr | SDA and SCL rise time | 120 | ns | ||
tf | SDA and SCL fall time | 20 × (IOVDD / 5.5 V) | 120 | ns | |
tSU;STO | Setup time for STOP condition | 0.26 | μs | ||
tBUF | Bus free time between a STOP and START condition | 0.5 | μs |