ZHCSLS0B July   2022  – April 2024 TPS929240-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Bias and Power
        1. 6.3.1.1 Power Bias (VBAT)
        2. 6.3.1.2 5V Low-Drop-Out Linear Regulator (VLDO)
        3. 6.3.1.3 Undervoltage Lockout (UVLO) and Power-On-Reset (POR)
        4. 6.3.1.4 Power Supply (SUPPLY)
        5. 6.3.1.5 Programmable Low Supply Warning
      2. 6.3.2 Constant Current Output
        1. 6.3.2.1 Reference Current with External Resistor (REF)
        2. 6.3.2.2 64-Step Programmable High-Side Constant-Current Output
      3. 6.3.3 PWM Dimming
        1. 6.3.3.1 PWM Generator
        2. 6.3.3.2 PWM Dimming Frequency
        3. 6.3.3.3 Blank Time
        4. 6.3.3.4 Phase Shift PWM Dimming
        5. 6.3.3.5 Linear Brightness Control
        6. 6.3.3.6 Exponential Brightness Control
      4. 6.3.4 FAIL-SAFE State Operation
      5. 6.3.5 On-Chip, 8-Bit, Analog-to-Digital Converter (ADC)
        1. 6.3.5.1 Minimum On Time for ADC Measurement
        2. 6.3.5.2 ADC Auto Scan
        3. 6.3.5.3 ADC Error
      6. 6.3.6 Diagnostic and Protection in NORMAL State
        1. 6.3.6.1  VBAT Undervoltage Lockout Diagnostics in NORMAL state
        2. 6.3.6.2  Low-Supply Warning Diagnostics in NORMAL State
        3. 6.3.6.3  Supply Undervoltage Diagnostics in NORMAL State
        4. 6.3.6.4  Reference Diagnostics in NORMAL state
        5. 6.3.6.5  Pre-Thermal Warning in NORMAL state
        6. 6.3.6.6  Overtemperature Protection in NORMAL state
        7. 6.3.6.7  Overtemperature Shutdown in NORMAL state
        8. 6.3.6.8  LED Open-Circuit Diagnostics in NORMAL state
        9. 6.3.6.9  LED Short-Circuit Diagnostics in NORMAL state
        10. 6.3.6.10 Single-LED Short-Circuit Detection in NORMAL state
        11. 6.3.6.11 EEPROM CRC Error in NORMAL state
        12. 6.3.6.12 Communication Loss Diagnostic in NORMAL State
        13. 6.3.6.13 Fault Masking in NORMAL state
        14.       53
      7. 6.3.7 Diagnostic and Protection in FAIL-SAFE states
        1. 6.3.7.1  Supply Undervoltage Lockout Diagnostics in FAIL-SAFE states
        2. 6.3.7.2  Low-Supply Warning Diagnostics in FAIL-SAFE states
        3. 6.3.7.3  Supply Undervoltage Diagnostics in FAIL-SAFE State
        4. 6.3.7.4  Reference Diagnostics in FAIL-SAFE states
        5. 6.3.7.5  Pre-Thermal Warning in FAIL-SAFE state
        6. 6.3.7.6  Overtemperature Protection in FAIL-SAFE state
        7. 6.3.7.7  Overtemperature Shutdown in FAIL-SAFE state
        8. 6.3.7.8  LED Open-Circuit Diagnostics in FAIL-SAFE state
        9. 6.3.7.9  LED Short-Circuit Diagnostics in FAIL-SAFE state
        10. 6.3.7.10 Single-LED Short-Circuit Detection in FAIL-SAFE state
        11. 6.3.7.11 EEPROM CRC Error in FAIL-SAFE State
        12. 6.3.7.12 Fault Masking in FAIL-SAFE state
        13.       Diagnostics Table in FAIL-SAFE State
      8. 6.3.8 OFAF Setup In FAIL-SAFE state
      9. 6.3.9 ERR Output
    4. 6.4 Device Functional Modes
      1. 6.4.1 POR State
      2. 6.4.2 INITIALIZATION state
      3. 6.4.3 NORMAL state
      4. 6.4.4 FAIL-SAFE state
      5. 6.4.5 PROGRAM state
    5. 6.5 Programming
      1. 6.5.1 FlexWire Protocol
        1. 6.5.1.1 Protocol Overview
        2. 6.5.1.2 UART Interface Address Setting
        3. 6.5.1.3 Status Response
        4. 6.5.1.4 Synchronization Byte
        5. 6.5.1.5 Device Address Byte
        6. 6.5.1.6 Register Address Byte
        7. 6.5.1.7 Data Frame
        8. 6.5.1.8 CRC Frame
        9. 6.5.1.9 Burst Mode
      2. 6.5.2 Registers Lock
      3. 6.5.3 Register Default Data
      4. 6.5.4 EEPROM Programming
        1. 6.5.4.1 Chip Selection by Pulling REF Pin High
        2. 6.5.4.2 Chip Selection by ADDR Pins Configuration
        3. 6.5.4.3 EEPROM Register Access and Burn
        4. 6.5.4.4 EEPROM PROGRAM State Exit
    6. 6.6 Register Maps
      1. 6.6.1 BRT Registers
      2. 6.6.2 IOUT Registers
      3. 6.6.3 CONF Registers
      4. 6.6.4 CTRL Registers
      5. 6.6.5 FLAG Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Smart Rear Lamp with Distributed LED Drivers
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.6.1 BRT Registers

Table 6-19 lists the memory-mapped registers for the BRT registers. All register offset addresses not listed in Table 6-19 should be considered as reserved locations and the register contents should not be modified.

Control Register

Table 6-19 BRT Registers
OffsetAcronymRegister NameSection
0hPWMMA08-MSB Output PWM Duty-cycle Setting for OUTA0Go
1hPWMMA18-MSB Output PWM Duty-cycle Setting for OUTA1Go
2hPWMMA28-MSB Output PWM Duty-cycle Setting for OUTA2Go
3hPWMMB08-MSB Output PWM Duty-cycle Setting for OUTB0Go
4hPWMMB18-MSB Output PWM Duty-cycle Setting for OUTB1Go
5hPWMMB28-MSB Output PWM Duty-cycle Setting for OUTB2Go
6hPWMMC08-MSB Output PWM Duty-cycle Setting for OUTC0Go
7hPWMMC18-MSB Output PWM Duty-cycle Setting for OUTC1Go
8hPWMMC28-MSB Output PWM Duty-cycle Setting for OUTC2Go
9hPWMMD08-MSB Output PWM Duty-cycle Setting for OUTD0Go
AhPWMMD18-MSB Output PWM Duty-cycle Setting for OUTD1Go
BhPWMMD28-MSB Output PWM Duty-cycle Setting for OUTD2Go
ChPWMME08-MSB Output PWM Duty-cycle Setting for OUTE0Go
DhPWMME18-MSB Output PWM Duty-cycle Setting for OUTE1Go
EhPWMME28-MSB Output PWM Duty-cycle Setting for OUTE2Go
FhPWMMF08-MSB Output PWM Duty-cycle Setting for OUTF0Go
10hPWMMF18-MSB Output PWM Duty-cycle Setting for OUTF1Go
11hPWMMF28-MSB Output PWM Duty-cycle Setting for OUTF2Go
12hPWMMG08-MSB Output PWM Duty-cycle Setting for OUTG0Go
13hPWMMG18-MSB Output PWM Duty-cycle Setting for OUTG1Go
14hPWMMG28-MSB Output PWM Duty-cycle Setting for OUTG2Go
15hPWMMH08-MSB Output PWM Duty-cycle Setting for OUTH0Go
16hPWMMH18-MSB Output PWM Duty-cycle Setting for OUTH1Go
17hPWMMH28-MSB Output PWM Duty-cycle Setting for OUTH2Go
20hPWMLA04-LSB Output PWM Duty-cycle Setting for OUTA0Go
21hPWMLA14-LSB Output PWM Duty-cycle Setting for OUTA1Go
22hPWMLA24-LSB Output PWM Duty-cycle Setting for OUTA2Go
23hPWMLB04-LSB Output PWM Duty-cycle Setting for OUTB0Go
24hPWMLB14-LSB Output PWM Duty-cycle Setting for OUTB1Go
25hPWMLB24-LSB Output PWM Duty-cycle Setting for OUTB2Go
26hPWMLC04-LSB Output PWM Duty-cycle Setting for OUTC0Go
27hPWMLC14-LSB Output PWM Duty-cycle Setting for OUTC1Go
28hPWMLC24-LSB Output PWM Duty-cycle Setting for OUTC2Go
29hPWMLD04-LSB Output PWM Duty-cycle Setting for OUTD0Go
2AhPWMLD14-LSB Output PWM Duty-cycle Setting for OUTD1Go
2BhPWMLD24-LSB Output PWM Duty-cycle Setting for OUTD2Go
2ChPWMLE04-LSB Output PWM Duty-cycle Setting for OUTE0Go
2DhPWMLE14-LSB Output PWM Duty-cycle Setting for OUTE1Go
2EhPWMLE24-LSB Output PWM Duty-cycle Setting for OUTE2Go
2FhPWMLF04-LSB Output PWM Duty-cycle Setting for OUTF0Go
30hPWMLF14-LSB Output PWM Duty-cycle Setting for OUTF1Go
31hPWMLF24-LSB Output PWM Duty-cycle Setting for OUTF2Go
32hPWMLG04-LSB Output PWM Duty-cycle Setting for OUTG0Go
33hPWMLG14-LSB Output PWM Duty-cycle Setting for OUTG1Go
34hPWMLG24-LSB Output PWM Duty-cycle Setting for OUTG2Go
35hPWMLH04-LSB Output PWM Duty-cycle Setting for OUTH0Go
36hPWMLH14-LSB Output PWM Duty-cycle Setting for OUTH1Go
37hPWMLH24-LSB Output PWM Duty-cycle Setting for OUTH2Go
40hOUTEN0OUTAn, OUTBn Enable SettingGo
41hOUTEN1OUTCn, OUTDn Enable SettingGo
42hOUTEN2OUTEn, OUTFn Enable SettingGo
43hOUTEN3OUTGn, OUTHn Enable SettingGo
44hPWMSHAREPWM Duty-cycle Sharing for All Enabled OutputGo

Complex bit access types are encoded to fit into small table cells. Table 6-20 shows the codes that are used for access types in this section.

Table 6-20 BRT Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.6.1.1 PWMMA0 Register (Offset = 0h) [Reset = 00h]

PWMMA0 is shown in Figure 6-19 and described in Table 6-21.

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Figure 6-19 PWMMA0 Register
76543210
PWMOUTA0
R/W-0h
Table 6-21 PWMMA0 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTA0R/W0h 8-MSB output PWM duty-cycle setting for OUTA0

6.6.1.2 PWMMA1 Register (Offset = 1h) [Reset = 00h]

PWMMA1 is shown in Figure 6-20 and described in Table 6-22.

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Figure 6-20 PWMMA1 Register
76543210
PWMOUTA1
R/W-0h
Table 6-22 PWMMA1 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTA1R/W0h 8-MSB output PWM duty-cycle setting for OUTA1

6.6.1.3 PWMMA2 Register (Offset = 2h) [Reset = 00h]

PWMMA2 is shown in Figure 6-21 and described in Table 6-23.

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Figure 6-21 PWMMA2 Register
76543210
PWMOUTA2
R/W-0h
Table 6-23 PWMMA2 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTA2R/W0h 8-MSB output PWM duty-cycle setting for OUTA2

6.6.1.4 PWMMB0 Register (Offset = 3h) [Reset = 00h]

PWMMB0 is shown in Figure 6-22 and described in Table 6-24.

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Figure 6-22 PWMMB0 Register
76543210
PWMOUTB0
R/W-0h
Table 6-24 PWMMB0 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTB0R/W0h 8-MSB output PWM duty-cycle setting for OUTB0

6.6.1.5 PWMMB1 Register (Offset = 4h) [Reset = 00h]

PWMMB1 is shown in Figure 6-23 and described in Table 6-25.

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Figure 6-23 PWMMB1 Register
76543210
PWMOUTB1
R/W-0h
Table 6-25 PWMMB1 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTB1R/W0h 8-MSB output PWM duty-cycle setting for OUTB1

6.6.1.6 PWMMB2 Register (Offset = 5h) [Reset = 00h]

PWMMB2 is shown in Figure 6-24 and described in Table 6-26.

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Figure 6-24 PWMMB2 Register
76543210
PWMOUTB2
R/W-0h
Table 6-26 PWMMB2 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTB2R/W0h 8-MSB output PWM duty-cycle setting for OUTB2

6.6.1.7 PWMMC0 Register (Offset = 6h) [Reset = 00h]

PWMMC0 is shown in Figure 6-25 and described in Table 6-27.

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Figure 6-25 PWMMC0 Register
76543210
PWMOUTC0
R/W-0h
Table 6-27 PWMMC0 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTC0R/W0h 8-MSB output PWM duty-cycle setting for OUTC0

6.6.1.8 PWMMC1 Register (Offset = 7h) [Reset = 00h]

PWMMC1 is shown in Figure 6-26 and described in Table 6-28.

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Figure 6-26 PWMMC1 Register
76543210
PWMOUTC1
R/W-0h
Table 6-28 PWMMC1 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTC1R/W0h 8-MSB output PWM duty-cycle setting for OUTC1

6.6.1.9 PWMMC2 Register (Offset = 8h) [Reset = 00h]

PWMMC2 is shown in Figure 6-27 and described in Table 6-29.

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Figure 6-27 PWMMC2 Register
76543210
PWMOUTC2
R/W-0h
Table 6-29 PWMMC2 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTC2R/W0h 8-MSB output PWM duty-cycle setting for OUTC2

6.6.1.10 PWMMD0 Register (Offset = 9h) [Reset = 00h]

PWMMD0 is shown in Figure 6-28 and described in Table 6-30.

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Figure 6-28 PWMMD0 Register
76543210
PWMOUTD0
R/W-0h
Table 6-30 PWMMD0 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTD0R/W0h 8-MSB output PWM duty-cycle setting for OUTD0

6.6.1.11 PWMMD1 Register (Offset = Ah) [Reset = 00h]

PWMMD1 is shown in Figure 6-29 and described in Table 6-31.

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Figure 6-29 PWMMD1 Register
76543210
PWMOUTD1
R/W-0h
Table 6-31 PWMMD1 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTD1R/W0h 8-MSB output PWM duty-cycle setting for OUTD1

6.6.1.12 PWMMD2 Register (Offset = Bh) [Reset = 00h]

PWMMD2 is shown in Figure 6-30 and described in Table 6-32.

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Figure 6-30 PWMMD2 Register
76543210
PWMOUTD2
R/W-0h
Table 6-32 PWMMD2 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTD2R/W0h 8-MSB output PWM duty-cycle setting for OUTD2

6.6.1.13 PWMME0 Register (Offset = Ch) [Reset = 00h]

PWMME0 is shown in Figure 6-31 and described in Table 6-33.

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Figure 6-31 PWMME0 Register
76543210
PWMOUTE0
R/W-0h
Table 6-33 PWMME0 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTE0R/W0h 8-MSB output PWM duty-cycle setting for OUTE0

6.6.1.14 PWMME1 Register (Offset = Dh) [Reset = 00h]

PWMME1 is shown in Figure 6-32 and described in Table 6-34.

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Figure 6-32 PWMME1 Register
76543210
PWMOUTE1
R/W-0h
Table 6-34 PWMME1 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTE1R/W0h 8-MSB output PWM duty-cycle setting for OUTE1

6.6.1.15 PWMME2 Register (Offset = Eh) [Reset = 00h]

PWMME2 is shown in Figure 6-33 and described in Table 6-35.

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Figure 6-33 PWMME2 Register
76543210
PWMOUTE2
R/W-0h
Table 6-35 PWMME2 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTE2R/W0h 8-MSB output PWM duty-cycle setting for OUTE2

6.6.1.16 PWMMF0 Register (Offset = Fh) [Reset = 00h]

PWMMF0 is shown in Figure 6-34 and described in Table 6-36.

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Figure 6-34 PWMMF0 Register
76543210
PWMOUTF0
R/W-0h
Table 6-36 PWMMF0 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTF0R/W0h 8-MSB output PWM duty-cycle setting for OUTF0

6.6.1.17 PWMMF1 Register (Offset = 10h) [Reset = 00h]

PWMMF1 is shown in Figure 6-35 and described in Table 6-37.

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Figure 6-35 PWMMF1 Register
76543210
PWMOUTF1
R/W-0h
Table 6-37 PWMMF1 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTF1R/W0h 8-MSB output PWM duty-cycle setting for OUTF1

6.6.1.18 PWMMF2 Register (Offset = 11h) [Reset = 00h]

PWMMF2 is shown in Figure 6-36 and described in Table 6-38.

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Figure 6-36 PWMMF2 Register
76543210
PWMOUTF2
R/W-0h
Table 6-38 PWMMF2 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTF2R/W0h 8-MSB output PWM duty-cycle setting for OUTF2

6.6.1.19 PWMMG0 Register (Offset = 12h) [Reset = 00h]

PWMMG0 is shown in Figure 6-37 and described in Table 6-39.

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Figure 6-37 PWMMG0 Register
76543210
PWMOUTG0
R/W-0h
Table 6-39 PWMMG0 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTG0R/W0h 8-MSB output PWM duty-cycle setting for OUTG0

6.6.1.20 PWMMG1 Register (Offset = 13h) [Reset = 00h]

PWMMG1 is shown in Figure 6-38 and described in Table 6-40.

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Figure 6-38 PWMMG1 Register
76543210
PWMOUTG1
R/W-0h
Table 6-40 PWMMG1 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTG1R/W0h 8-MSB output PWM duty-cycle setting for OUTG1

6.6.1.21 PWMMG2 Register (Offset = 14h) [Reset = 00h]

PWMMG2 is shown in Figure 6-39 and described in Table 6-41.

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Figure 6-39 PWMMG2 Register
76543210
PWMOUTG2
R/W-0h
Table 6-41 PWMMG2 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTG2R/W0h 8-MSB output PWM duty-cycle setting for OUTG2

6.6.1.22 PWMMH0 Register (Offset = 15h) [Reset = 00h]

PWMMH0 is shown in Figure 6-40 and described in Table 6-42.

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Figure 6-40 PWMMH0 Register
76543210
PWMOUTH0
R/W-0h
Table 6-42 PWMMH0 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTH0R/W0h 8-MSB output PWM duty-cycle setting for OUTH0

6.6.1.23 PWMMH1 Register (Offset = 16h) [Reset = 00h]

PWMMH1 is shown in Figure 6-41 and described in Table 6-43.

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Figure 6-41 PWMMH1 Register
76543210
PWMOUTH1
R/W-0h
Table 6-43 PWMMH1 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTH1R/W0h 8-MSB output PWM duty-cycle setting for OUTH1

6.6.1.24 PWMMH2 Register (Offset = 17h) [Reset = 00h]

PWMMH2 is shown in Figure 6-42 and described in Table 6-44.

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Figure 6-42 PWMMH2 Register
76543210
PWMOUTH2
R/W-0h
Table 6-44 PWMMH2 Register Field Descriptions
BitFieldTypeResetDescription
7-0PWMOUTH2R/W0h 8-MSB output PWM duty-cycle setting for OUTH2

6.6.1.25 PWMLA0 Register (Offset = 20h) [Reset = 00h]

PWMLA0 is shown in Figure 6-43 and described in Table 6-45.

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Figure 6-43 PWMLA0 Register
76543210
RESERVEDPWMLOWOUTA0
R-0hR/W-0h
Table 6-45 PWMLA0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTA0R/W0h 4-LSB output PWM duty-cycle setting for OUTA0

6.6.1.26 PWMLA1 Register (Offset = 21h) [Reset = 00h]

PWMLA1 is shown in Figure 6-44 and described in Table 6-46.

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Figure 6-44 PWMLA1 Register
76543210
RESERVEDPWMLOWOUTA1
R-0hR/W-0h
Table 6-46 PWMLA1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTA1R/W0h 4-LSB output PWM duty-cycle setting for OUTA1

6.6.1.27 PWMLA2 Register (Offset = 22h) [Reset = 00h]

PWMLA2 is shown in Figure 6-45 and described in Table 6-47.

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Figure 6-45 PWMLA2 Register
76543210
RESERVEDPWMLOWOUTA2
R-0hR/W-0h
Table 6-47 PWMLA2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTA2R/W0h 4-LSB output PWM duty-cycle setting for OUTA2

6.6.1.28 PWMLB0 Register (Offset = 23h) [Reset = 00h]

PWMLB0 is shown in Figure 6-46 and described in Table 6-48.

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Figure 6-46 PWMLB0 Register
76543210
RESERVEDPWMLOWOUTB0
R-0hR/W-0h
Table 6-48 PWMLB0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTB0R/W0h 4-LSB output PWM duty-cycle setting for OUTB0

6.6.1.29 PWMLB1 Register (Offset = 24h) [Reset = 00h]

PWMLB1 is shown in Figure 6-47 and described in Table 6-49.

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Figure 6-47 PWMLB1 Register
76543210
RESERVEDPWMLOWOUTB1
R-0hR/W-0h
Table 6-49 PWMLB1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTB1R/W0h 4-LSB output PWM duty-cycle setting for OUTB1

6.6.1.30 PWMLB2 Register (Offset = 25h) [Reset = 00h]

PWMLB2 is shown in Figure 6-48 and described in Table 6-50.

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Figure 6-48 PWMLB2 Register
76543210
RESERVEDPWMLOWOUTB2
R-0hR/W-0h
Table 6-50 PWMLB2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTB2R/W0h 4-LSB output PWM duty-cycle setting for OUTB2

6.6.1.31 PWMLC0 Register (Offset = 26h) [Reset = 00h]

PWMLC0 is shown in Figure 6-49 and described in Table 6-51.

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Figure 6-49 PWMLC0 Register
76543210
RESERVEDPWMLOWOUTC0
R-0hR/W-0h
Table 6-51 PWMLC0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTC0R/W0h 4-LSB output PWM duty-cycle setting for OUTC0

6.6.1.32 PWMLC1 Register (Offset = 27h) [Reset = 00h]

PWMLC1 is shown in Figure 6-50 and described in Table 6-52.

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Figure 6-50 PWMLC1 Register
76543210
RESERVEDPWMLOWOUTC1
R-0hR/W-0h
Table 6-52 PWMLC1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTC1R/W0h 4-LSB output PWM duty-cycle setting for OUTC1

6.6.1.33 PWMLC2 Register (Offset = 28h) [Reset = 00h]

PWMLC2 is shown in Figure 6-51 and described in Table 6-53.

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Figure 6-51 PWMLC2 Register
76543210
RESERVEDPWMLOWOUTC2
R-0hR/W-0h
Table 6-53 PWMLC2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTC2R/W0h 4-LSB output PWM duty-cycle setting for OUTC2

6.6.1.34 PWMLD0 Register (Offset = 29h) [Reset = 00h]

PWMLD0 is shown in Figure 6-52 and described in Table 6-54.

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Figure 6-52 PWMLD0 Register
76543210
RESERVEDPWMLOWOUTD0
R-0hR/W-0h
Table 6-54 PWMLD0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTD0R/W0h 4-LSB output PWM duty-cycle setting for OUTD0

6.6.1.35 PWMLD1 Register (Offset = 2Ah) [Reset = 00h]

PWMLD1 is shown in Figure 6-53 and described in Table 6-55.

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Figure 6-53 PWMLD1 Register
76543210
RESERVEDPWMLOWOUTD1
R-0hR/W-0h
Table 6-55 PWMLD1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTD1R/W0h 4-LSB output PWM duty-cycle setting for OUTD1

6.6.1.36 PWMLD2 Register (Offset = 2Bh) [Reset = 00h]

PWMLD2 is shown in Figure 6-54 and described in Table 6-56.

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Figure 6-54 PWMLD2 Register
76543210
RESERVEDPWMLOWOUTD2
R-0hR/W-0h
Table 6-56 PWMLD2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTD2R/W0h 4-LSB output PWM duty-cycle setting for OUTD2

6.6.1.37 PWMLE0 Register (Offset = 2Ch) [Reset = 00h]

PWMLE0 is shown in Figure 6-55 and described in Table 6-57.

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Figure 6-55 PWMLE0 Register
76543210
RESERVEDPWMLOWOUTE0
R-0hR/W-0h
Table 6-57 PWMLE0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTE0R/W0h 4-LSB output PWM duty-cycle setting for OUTE0

6.6.1.38 PWMLE1 Register (Offset = 2Dh) [Reset = 00h]

PWMLE1 is shown in Figure 6-56 and described in Table 6-58.

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Figure 6-56 PWMLE1 Register
76543210
RESERVEDPWMLOWOUTE1
R-0hR/W-0h
Table 6-58 PWMLE1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTE1R/W0h 4-LSB output PWM duty-cycle setting for OUTE1

6.6.1.39 PWMLE2 Register (Offset = 2Eh) [Reset = 00h]

PWMLE2 is shown in Figure 6-57 and described in Table 6-59.

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Figure 6-57 PWMLE2 Register
76543210
RESERVEDPWMLOWOUTE2
R-0hR/W-0h
Table 6-59 PWMLE2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTE2R/W0h 4-LSB output PWM duty-cycle setting for OUTE2

6.6.1.40 PWMLF0 Register (Offset = 2Fh) [Reset = 00h]

PWMLF0 is shown in Figure 6-58 and described in Table 6-60.

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Figure 6-58 PWMLF0 Register
76543210
RESERVEDPWMLOWOUTF0
R-0hR/W-0h
Table 6-60 PWMLF0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTF0R/W0h 4-LSB output PWM duty-cycle setting for OUTF0

6.6.1.41 PWMLF1 Register (Offset = 30h) [Reset = 00h]

PWMLF1 is shown in Figure 6-59 and described in Table 6-61.

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Figure 6-59 PWMLF1 Register
76543210
RESERVEDPWMLOWOUTF1
R-0hR/W-0h
Table 6-61 PWMLF1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTF1R/W0h 4-LSB output PWM duty-cycle setting for OUTF1

6.6.1.42 PWMLF2 Register (Offset = 31h) [Reset = 00h]

PWMLF2 is shown in Figure 6-60 and described in Table 6-62.

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Figure 6-60 PWMLF2 Register
76543210
RESERVEDPWMLOWOUTF2
R-0hR/W-0h
Table 6-62 PWMLF2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTF2R/W0h 4-LSB output PWM duty-cycle setting for OUTF2

6.6.1.43 PWMLG0 Register (Offset = 32h) [Reset = 00h]

PWMLG0 is shown in Figure 6-61 and described in Table 6-63.

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Figure 6-61 PWMLG0 Register
76543210
RESERVEDPWMLOWOUTG0
R-0hR/W-0h
Table 6-63 PWMLG0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTG0R/W0h 4-LSB output PWM duty-cycle setting for OUTG0

6.6.1.44 PWMLG1 Register (Offset = 33h) [Reset = 00h]

PWMLG1 is shown in Figure 6-62 and described in Table 6-64.

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Figure 6-62 PWMLG1 Register
76543210
RESERVEDPWMLOWOUTG1
R-0hR/W-0h
Table 6-64 PWMLG1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTG1R/W0h 4-LSB output PWM duty-cycle setting for OUTG1

6.6.1.45 PWMLG2 Register (Offset = 34h) [Reset = 00h]

PWMLG2 is shown in Figure 6-63 and described in Table 6-65.

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Figure 6-63 PWMLG2 Register
76543210
RESERVEDPWMLOWOUTG2
R-0hR/W-0h
Table 6-65 PWMLG2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTG2R/W0h 4-LSB output PWM duty-cycle setting for OUTG2

6.6.1.46 PWMLH0 Register (Offset = 35h) [Reset = 00h]

PWMLH0 is shown in Figure 6-64 and described in Table 6-66.

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Figure 6-64 PWMLH0 Register
76543210
RESERVEDPWMLOWOUTH0
R-0hR/W-0h
Table 6-66 PWMLH0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTH0R/W0h 4-LSB output PWM duty-cycle setting for OUTH0

6.6.1.47 PWMLH1 Register (Offset = 36h) [Reset = 00h]

PWMLH1 is shown in Figure 6-65 and described in Table 6-67.

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Figure 6-65 PWMLH1 Register
76543210
RESERVEDPWMLOWOUTH1
R-0hR/W-0h
Table 6-67 PWMLH1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTH1R/W0h 4-LSB output PWM duty-cycle setting for OUTH1

6.6.1.48 PWMLH2 Register (Offset = 37h) [Reset = 00h]

PWMLH2 is shown in Figure 6-66 and described in Table 6-68.

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Figure 6-66 PWMLH2 Register
76543210
RESERVEDPWMLOWOUTH2
R-0hR/W-0h
Table 6-68 PWMLH2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0PWMLOWOUTH2R/W0h 4-LSB output PWM duty-cycle setting for OUTH2

6.6.1.49 OUTEN0 Register (Offset = 40h) [Reset = 00h]

OUTEN0 is shown in Figure 6-67 and described in Table 6-69.

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Figure 6-67 OUTEN0 Register
76543210
RESERVEDENOUTB2ENOUTB1ENOUTB0RESERVEDENOUTA2ENOUTA1ENOUTA0
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 6-69 OUTEN0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6ENOUTB2R/W0h Enable register for OUTB2
0h = Disabled
1h = Enabled
5ENOUTB1R/W0h Enable register for OUTB1
0h = Disabled
1h = Enabled
4ENOUTB0R/W0h Enable register for OUTB0
0h = Disabled
1h = Enabled
3RESERVEDR0h Reserved
2ENOUTA2R/W0h Enable register for OUTA2
0h = Disabled
1h = Enabled
1ENOUTA1R/W0h Enable register for OUTA1
0h = Disabled
1h = Enabled
0ENOUTA0R/W0h Enable register for OUTA0
0h = Disabled
1h = Enabled

6.6.1.50 OUTEN1 Register (Offset = 41h) [Reset = 00h]

OUTEN1 is shown in Figure 6-68 and described in Table 6-70.

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Figure 6-68 OUTEN1 Register
76543210
RESERVEDENOUTD2ENOUTD1ENOUTD0RESERVEDENOUTC2ENOUTC1ENOUTC0
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 6-70 OUTEN1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6ENOUTD2R/W0h Enable register for OUTD2
0h = Disabled
1h = Enabled
5ENOUTD1R/W0h Enable register for OUTD1
0h = Disabled
1h = Enabled
4ENOUTD0R/W0h Enable register for OUTD0
0h = Disabled
1h = Enabled
3RESERVEDR0h Reserved
2ENOUTC2R/W0h Enable register for OUTC2
0h = Disabled
1h = Enabled
1ENOUTC1R/W0h Enable register for OUTC1
0h = Disabled
1h = Enabled
0ENOUTC0R/W0h Enable register for OUTC0
0h = Disabled
1h = Enabled

6.6.1.51 OUTEN2 Register (Offset = 42h) [Reset = 00h]

OUTEN2 is shown in Figure 6-69 and described in Table 6-71.

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Figure 6-69 OUTEN2 Register
76543210
RESERVEDENOUTF2ENOUTF1ENOUTF0RESERVEDENOUTE2ENOUTE1ENOUTE0
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 6-71 OUTEN2 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6ENOUTF2R/W0h Enable register for OUTF2
0h = Disabled
1h = Enabled
5ENOUTF1R/W0h Enable register for OUTF1
0h = Disabled
1h = Enabled
4ENOUTF0R/W0h Enable register for OUTF0
0h = Disabled
1h = Enabled
3RESERVEDR0h Reserved
2ENOUTE2R/W0h Enable register for OUTE2
0h = Disabled
1h = Enabled
1ENOUTE1R/W0h Enable register for OUTE1
0h = Disabled
1h = Enabled
0ENOUTE0R/W0h Enable register for OUTE0
0h = Disabled
1h = Enabled

6.6.1.52 OUTEN3 Register (Offset = 43h) [Reset = 00h]

OUTEN3 is shown in Figure 6-70 and described in Table 6-72.

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Figure 6-70 OUTEN3 Register
76543210
RESERVEDENOUTH2ENOUTH1ENOUTH0RESERVEDENOUTG2ENOUTG1ENOUTG0
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 6-72 OUTEN3 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6ENOUTH2R/W0h Enable register for OUTH2
0h = Disabled
1h = Enabled
5ENOUTH1R/W0h Enable register for OUTH1
0h = Disabled
1h = Enabled
4ENOUTH0R/W0h Enable register for OUTH0
0h = Disabled
1h = Enabled
3RESERVEDR0h Reserved
2ENOUTG2R/W0h Enable register for OUTG2
0h = Disabled
1h = Enabled
1ENOUTG1R/W0h Enable register for OUTG1
0h = Disabled
1h = Enabled
0ENOUTG0R/W0h Enable register for OUTG0
0h = Disabled
1h = Enabled

6.6.1.53 PWMSHARE Register (Offset = 44h) [Reset = 00h]

PWMSHARE is shown in Figure 6-71 and described in Table 6-73.

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Figure 6-71 PWMSHARE Register
76543210
RESERVEDSHAREPWM
R-0hR/W-0h
Table 6-73 PWMSHARE Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0SHAREPWMR/W0h Set all Output PWM duty-cyce same to OUTA0
0~Eh = Each output PWM duty-cycle is set independently
Fh = All output PWM duty-cycle set to same to OUTA0