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  • IWR6843AOP 单芯片 60GHz 至 64GHz 毫米波传感器封装天线 (AOP)

    • ZHCSLB7B April   2020  – July 2022 IWR6843AOP

      PRODUCTION DATA  

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  • IWR6843AOP 单芯片 60GHz 至 64GHz 毫米波传感器封装天线 (AOP)
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Pin Functions - Digital and Analog [ALP Package]
    3. 7.3 Pin Attributes
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
    6. 8.6  Power Consumption Summary
    7. 8.7  RF Specification
    8. 8.8  CPU Specifications
    9. 8.9  Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1  Antenna Radiation Patterns
        1. 8.10.1.1 Antenna Radiation Patterns for Receiver
        2. 8.10.1.2 Antenna Radiation Patterns for Transmitter
      2. 8.10.2  Antenna Positions
      3. 8.10.3  Power Supply Sequencing and Reset Timing
      4. 8.10.4  Input Clocks and Oscillators
        1. 8.10.4.1 Clock Specifications
      5. 8.10.5  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.10.5.1 Peripheral Description
        2. 8.10.5.2 MibSPI Transmit and Receive RAM Organization
          1. 8.10.5.2.1 SPI Timing Conditions
          2. 8.10.5.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
          3. 8.10.5.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
        3. 8.10.5.3 SPI Peripheral Mode I/O Timings
          1. 8.10.5.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 8.10.5.4 Typical Interface Protocol Diagram (Peripheral Mode)
      6. 8.10.6  LVDS Interface Configuration
        1. 8.10.6.1 LVDS Interface Timings
      7. 8.10.7  General-Purpose Input/Output
        1. 8.10.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 8.10.8  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 8.10.8.1 Dynamic Characteristics for the CANx TX and RX Pins
      9. 8.10.9  Serial Communication Interface (SCI)
        1. 8.10.9.1 SCI Timing Requirements
      10. 8.10.10 Inter-Integrated Circuit Interface (I2C)
        1. 8.10.10.1 I2C Timing Requirements (1)
      11. 8.10.11 Quad Serial Peripheral Interface (QSPI)
        1. 8.10.11.1 QSPI Timing Conditions
        2. 8.10.11.2 Timing Requirements for QSPI Input (Read) Timings (1) (1)
        3. 8.10.11.3 QSPI Switching Characteristics
      12. 8.10.12 ETM Trace Interface
        1. 8.10.12.1 ETMTRACE Timing Conditions
        2. 8.10.12.2 ETM TRACE Switching Characteristics
      13. 8.10.13 Data Modification Module (DMM)
        1. 8.10.13.1 DMM Timing Requirements
      14. 8.10.14 JTAG Interface
        1. 8.10.14.1 JTAG Timing Conditions
        2. 8.10.14.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.10.14.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Processor Subsystem
      3. 9.3.3 Host Interface
      4. 9.3.4 Main Subsystem Cortex-R4F
      5. 9.3.5 DSP Subsystem
      6. 9.3.6 Hardware Accelerator
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Channels (Service) for User Application
        1. 9.4.1.1 GP-ADC Parameter
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
      1. 10.1.1 Error Signaling Module
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
  14. 重要声明
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DATA SHEET

IWR6843AOP 单芯片 60GHz 至 64GHz 毫米波传感器封装天线 (AOP)

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • FMCW 收发器
    • 集成 4 个接收器和 3 个发送器的封装天线 (AOP)
    • 集成 PLL、发送器、接收器、基带和 ADC
    • 60GHz 至 64GHz 的覆盖范围，具有 4GHz 的连续带宽
    • 支持 6 位移相器，可实现 TX 波束形成
    • 基于分数 N PLL 的超精确线性调频脉冲引擎
  • 内置校准和自检
    • ®基于 Arm®Cortex®-R4F 的无线电控制系统
    • 内置固件 (ROM)
    • 针对工艺和温度进行自校准的系统
    • 在符合功能安全标准的器件上提供嵌入式自监控，无需主机处理器参与
  • 用于高级信号处理的 C674x DSP
  • 存储器压缩
  • 用于 FFT、滤波和 CFAR 处理的硬件加速器
  • 用于物体检测和接口控制的 ARM-R4F 微控制器
    • 支持自主模式（从 QSPI 闪存加载用户应用）
  • 具有 ECC 的内部存储器
    • 1.75MB，分为 MSS 程序 RAM (512KB)、MSS 数据 RAM (192KB)、DSP L1 RAM (64KB) 和 L2 RAM (256KB) 以及 L3 雷达数据立方体 RAM (768KB)
    • 技术参考手册包括允许的大小修改
  • 器件安全（在部分器件型号上）
    • 支持经过身份验证和加密的安全引导
    • 具有密钥撤销功能的客户可编程根密钥、对称密钥（256 位）、非对称密钥（最高 RSA-2K）
    • 加密软件加速器 – PKA、AES（最高 256 位）、SHA（最高 256 位）、TRNG/DRGB
  • 为用户应用提供的其他接口
    • 多达 6 个 ADC 通道（低采样率监控）
    • 多达 2 个 SPI 端口
    • 多达 2 个 UART
    • 1 个 CAN-FD 接口
    • I2C
    • GPIO
    • 用于原始 ADC 数据和调试仪表的双通道 LVDS 接口
  • 符合功能安全标准
    • 专为功能安全应用开发
    • 文档有助于使 IEC 61508 功能安全系统设计符合 SIL-3 级标准
    • 硬件完整性高达 SIL-2 级
    • 安全相关认证
      • 经 TUV SUD 进行 IEC 61508 认证达到 SIL 2 级
  • 电源管理
    • 内置 LDO 网络，可增强 PSRR
    • I/O 支持双电压 3.3V/1.8V
  • 时钟源
    • 具有内部振荡器的 40.0MHz 晶体
    • 支持频率为 40MHz 的外部振荡器
    • 支持外部驱动、频率为 40MHz 的时钟（方波/正弦波）
  • 轻松的硬件设计
    • 0.8mm 间距、180 引脚 15mm × 15mm FCBGA 封装 (ALP)，可实现轻松组装和低成本 PCB 设计
    • 小尺寸解决方案
  • 运行条件
    • 结温范围：–40°C 至 105°C

2 应用

  • 用于测量距离、速度和角度的工业传感器
  • 楼宇自动化
  • 位移感应
  • 手势
  • 机器人
  • 交通监控
  • 接近和位置感应
  • 安全和监控
  • 工厂自动化安全防护装置
  • 人数统计
  • 运动检测
  • 占位检测

3 说明

IWR6843AOP 是一款封装天线 (AOP) 器件，是德州仪器 (TI) 的单芯片雷达器件系列的升级版。该器件在极小的封装中实现了出色的集成度，是适用于工业领域中的低功耗、自监控、超精确雷达系统的理想解决方案。当前可提供多个系列，包括功能安全合规型器件 (SIL2) 和非功能安全器件。

它集成了一个 DSP 子系统，该子系统包含 TI 用于雷达信号处理的高性能 C674x DSP。该器件包含一个 BIST 处理器子系统，该子系统负责无线电配置、控制和校准。此外，该器件还包含用于汽车连接的用户可编程 Arm Cortex-R4F。硬件加速器区块 (HWA) 可执行雷达处理，并减轻 DSP 上的负载，从而执行更高级的算法。简单编程模型更改可支持各种传感器应用，并且能够进行动态重新配置，从而实现多模式传感器。此外，该器件作为完整的平台解决方案进行提供，该解决方案包括硬件参考设计、软件驱动程序、样例配置、API 指南以及用户文档。

器件信息
器件型号(2) 封装(1) 封装尺寸 托盘/卷带包装
IWR6843ARQGALP FCBGA (180) 15mm × 15mm 托盘
IWR6843ARQGALPR FCBGA (180) 15mm × 15mm 卷带包装
IWR6843ARQSALP FCBGA (180) 15mm × 15mm 托盘
IWR6843ARQSALPR FCBGA (180) 15mm × 15mm 卷带包装
IWR6843ARBGALP(3) FCBGA (180) 15mm × 15mm 托盘
IWR6843ARBGALPR(3) FCBGA (180) 15mm × 15mm 卷带包装
(1) 如需更多信息，请参阅Section 13机械、封装和可订购信息。
(2) 如需更多信息，请参阅Section 12.1，器件命名规则。
(3) 功能安全合规型 SIL-2 器件可订购器件型号 (OPN)。

4 功能方框图

图 4-1 展示了器件的功能方框图

GUID-38A1821B-C7A9-445A-968A-5B43D4DD1CAD-low.gif 图 4-1 功能方框图

5 Revision History

Changes from May 1, 2021 to July 20, 2022 (from Revision A (April 2021) to Revision B (July 2022))

  • （特性）：更新了功能安全合规认证资料和相关细节；更新了有关器件安全的其他信息Go
  • （器件信息）：更新了 IWR6843AOP 器件的功能安全合规型 OPNGo
  • （说明）：更新/更改了“说明”以添加有关器件子系统的更多详细信息。Go
  • (Device Comparison): Removed a row on Functional-Safety compliance and instead added a table-note for this and LVDS Interface; Additional information on Device security addedGo
  • Updated/Changed Pin Attributes (ABL0161 Package) to match the AWR1642 deviceGo
  • Updated/Changed all instances of "CAN_FD_tx" to "Reserved" in Pin Attributes (ABL0161 Package)Go
  • Updated/Changed all instances of "CAN_FD_rx" to "Reserved" in Pin Attributes (ABL0161 Package)Go
  • Added two register tables after Pin AttributesGo
  • Updated/Changed PAD IO Control RegistersGo
  • Removed External Clock Electrical Characteristics tableGo
  • Updated/Changed External Clock Mode Specifications table to match AWR16Go
  • (Table. External Clock Mode Specifications): Revised frequency tolerance specs from +/-50 to +/-100 ppmGo
  • Peripheral Description: Added "The SPI uses a MibSPI Protocol by TI" to MibSPI peripheral descriptionGo
  • (QSPI Timings):Updated/Changed Setup Time from 7.3us to 5us and Hold Time from 1.5us to 1us for QSPI TimingsGo
  • (QSPI Timings): Updated/Changed Delay time, sclk falling edge to d[1] transition i.e. [Q6, Q9] from -3.5us to -2.5us (Min) and 7us to 4us (Max) in QSPI Switching CharacteristicsGo
  • Updated/Changed Host Interrupt bullet in Host InterfaceGo
  • Updated/changed "CAN" to "CAN-FD"Go
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect Functional Safety-Compliance; added a note for reference to safety related collateral Go
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect Functional Safety-Compliance; added a note for reference to safety related collateral Go

6 Device Comparison

Table 6-1 Device Features Comparison
FUNCTIONIWR6843AOP(1)IWR6843IWR1843IWR1642IWR1443
Antenna on Package (AOP)Yes— ———
Number of receivers44444
Number of transmitters3(2)3(2)3(2)23
RF frequency range60 to 64 GHz60 to 64 GHz76 to 81 GHz76 to 81 GHz76 to 81 GHz
On-chip memory1.75MB1.75MB2MB1.5MB576KB
Max I/F (Intermediate Frequency) (MHz)101010515
Max real sampling rate (Msps)25252512.537.5
Max complex sampling rate (Msps)12.512.512.56.2518.75
Device Security(3)YesYesYesYes—
Processors
MCU (R4F)YesYesYesYesYes
DSP (C674x)YesYesYesYes—
Peripherals
Serial Peripheral Interface (SPI) ports22221
Quad Serial Peripheral Interface (QSPI)YesYesYesYesYes
Inter-Integrated Circuit (I2C) interface11111
Controller Area Network (DCAN) interface——YesYesYes
Controller Area Network (CAN-FD) interfaceYesYesYes——
TraceYesYesYesYes—
PWMYesYesYesYes—
Hardware In Loop (HIL/DMM)YesYesYesYes—
GPADCYesYesYesYesYes
LVDS/Debug (4)YesYesYesYesYes
CSI2————Yes
Hardware acceleratorYesYesYes—Yes
1-V bypass modeYesYesYesYesYes
JTAGYesYesYesYesYes
Product statusProduct Preview (PP),
Advance Information (AI),
or Production Data (PD)		PD(5)PD(5)PD(5)PD(5)PD(5)
(1) Developed for Functional Safety applications, the device supports hardware integrity upto SIL-2. Refer to the related documentation for more details.
(2) 3 Tx Simultaneous operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply needs to be fed on the VOUT PA pin.
(3) Device security features including Secure Boot and Customer Programmable Keys are available in select devices for only select part variants as indicated by the Device Type identifier in Section 3, Device Information table.
(4) LVDS Interface is not a production Interface and is only used for debug.
(5) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty.

6.1 Related Products

For information about other devices in this family of products or related products see the links that follow.

    mmWave sensorsTI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less power using the smallest footprint mmWave sensor portfolio for industrial applications.
    mmWave IWRThe Texas Instruments IWRxxxx family of mmWave Sensors are highly integrated and built on RFCMOS technology operating in 76- to 81-GHz or 60- to 64-GHz frequency band. The devices have a closed-loop PLL for precise and linear chirp synthesis, includes a built-in radio processor (BIST) for RF calibration and safety monitoring. The devices have a very small-form factor, low power consumption, and are highly accurate. Industrial applications from long range to ultra short range can be realized using these devices.
    Companion products Review products that are frequently purchased or used in conjunction with this product.
    Reference designs The IWR6843 TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump-start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns.

7 Terminal Configuration and Functions

 
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