ZHCSK12A July 2019 – October 2019 TLV320ADC6140
PRODUCTION DATA.
This register is the GPI configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | GPI1_CFG[2:0] | Reserved | GPI2_CFG[2:0] | ||||
R-0h | R/W-0h | R-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Reserved | R | 0h | Reserved |
6-4 | GPI1_CFG[2:0] | R/W | 0h | IN1P_GPI1 (GPI1) configuration.
0d = GPI1 is disabled 1d = GPI1 is configured as a general-purpose input (GPI) 2d = GPI1 is configured as a master clock input (MCLK) 3d = GPI1 is configured as an ASI input for daisy-chain (SDIN) 4d = GPI1 is configured as a PDM data input for channel 1 and channel 2 (PDMDIN1) 5d = GPI1 is configured as a PDM data input for channel 3 and channel 4 (PDMDIN2) 6d = GPI1 is configured as a PDM data input for channel 5 and channel 6 (PDMDIN3) 7d = GPI1 is configured as a PDM data input for channel 7 and channel 8 (PDMDIN4) |
3 | Reserved | R | 0h | Reserved |
2-0 | GPI2_CFG[2:0] | R/W | 0h | IN2P_GPI2 (GPI2) configuration.
0d = GPI2 is disabled 1d = GPI2 is configured as a general-purpose input (GPI) 2d = GPI2 is configured as a master clock input (MCLK) 3d = GPI2 is configured as an ASI input for daisy-chain (SDIN) 4d = GPI2 is configured as a PDM data input for channel 1 and channel 2 (PDMDIN1) 5d = GPI2 is configured as a PDM data input for channel 3 and channel 4 (PDMDIN2) 6d = GPI2 is configured as a PDM data input for channel 5 and channel 6 (PDMDIN3) 7d = GPI2 is configured as a PDM data input for channel 7 and channel 8 (PDMDIN4) |