ZHCSJR3B February 2019 – November 2019 BQ25887
PRODUCTION DATA.
REG1D is shown in Figure 53 and described in Table 37.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Field | VBAT_ADC[15:8] |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | VBAT_ADC[15] | R | Yes | No | Sign bit: overall results reported in two's complement. | |
6 | VBAT_ADC[14] | R | Yes | No | 16384 mV | |
5 | VBAT_ADC[13] | R | Yes | No | 8192 mV | VBAT Voltage reading:
Range: 0 V – 10 V |
4 | VBAT_ADC[12] | R | Yes | No | 4096 mV | |
3 | VBAT_ADC[11] | R | Yes | No | 2048 mV | |
2 | VBAT_ADC[10] | R | Yes | No | 1024 mV | |
1 | VBAT_ADC[9] | R | Yes | No | 512 mV | |
0 | VBAT_ADC[8] | R | Yes | No | 256 mV |