ZHCSJR3B February 2019 – November 2019 BQ25887
PRODUCTION DATA.
REG18 is shown in Figure 48 and described in Table 32.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Field | IBUS_ADC[7:0] |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | IBUS_ADC[7] | R | Yes | No | 128 mA | VBUS Current Reading (positive current flows into VBUS pin, negative current flows out ot VBUS pin):
Range: 0 A – 4 A |
6 | IBUS_ADC[6] | R | Yes | No | 64 mA | |
5 | IBUS_ADC[5] | R | Yes | No | 32 mA | |
4 | IBUS_ADC[4] | R | Yes | No | 16 mA | |
3 | IBUS_ADC[3] | R | Yes | No | 8 mA | |
2 | IBUS_ADC[2] | R | Yes | No | 4 mA | |
1 | IBUS_ADC[1] | R | Yes | No | 2 mA | |
0 | IBUS_ADC[0] | R | Yes | No | 1 mA |