ZHCSJR3B February 2019 – November 2019 BQ25887
PRODUCTION DATA.
REG17 is shown in Figure 47 and described in Table 31.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Field | IBUS_ADC[15:8] |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | IBUS_ADC[15] | R | Yes | No | Sign bit: overall results reported in two's complement. | |
6 | IBUS_ADC[14] | R | Yes | No | 16384 mA | |
5 | IBUS_ADC[13] | R | Yes | No | 8192 mA | |
4 | IBUS_ADC[12] | R | Yes | No | 4096 mA | |
3 | IBUS_ADC[11] | R | Yes | No | 2048 mA | VBUS Current Reading (positive current flows into VBUS pin, negative current flows out ot VBUS pin):
Range: 0 A – 4 A |
2 | IBUS_ADC[10] | R | Yes | No | 1024 mA | |
1 | IBUS_ADC[9] | R | Yes | No | 512 mA | |
0 | IBUS_ADC[8] | R | Yes | No | 256 mA |