5 Pin Configuration and Functions

DLP5500 FYA Package149-Pin CPGA Series 450Bottom View

Figure 5-1 FYA Package149-Pin CPGA Series 450Bottom View

Table 5-1 Pin Functions

PIN⁽¹⁾		TYPE (I/O/P )	SIGNAL	DATA RATE⁽²⁾	INTERNAL TERM⁽³⁾	CLOCK	DESCRIPTION	TRACE (mils)⁽⁴⁾
NAME	NO.	TYPE (I/O/P )	SIGNAL	DATA RATE⁽²⁾	INTERNAL TERM⁽³⁾	CLOCK	DESCRIPTION	TRACE (mils)⁽⁴⁾
DATA INPUTS
D_AN1	G20	Input	LVCMOS	DDR	Differential	DCLK_A	Input data bus A (LVDS)	715
D_AP1	H20	Input	LVCMOS	DDR	Differential	DCLK_A		744
D_AN3	H19	Input	LVCMOS	DDR	Differential	DCLK_A		688
D_AP3	G19	Input	LVCMOS	DDR	Differential	DCLK_A		703
D_AN5	F18	Input	LVCMOS	DDR	Differential	DCLK_A		686
D_AP5	G18	Input	LVCMOS	DDR	Differential	DCLK_A		714
D_AN7	E18	Input	LVCMOS	DDR	Differential	DCLK_A		689
D_AP7	D18	Input	LVCMOS	DDR	Differential	DCLK_A		705
D_AN9	C20	Input	LVCMOS	DDR	Differential	DCLK_A		687
D_AP9	D20	Input	LVCMOS	DDR	Differential	DCLK_A		715
D_AN11	B18	Input	LVCMOS	DDR	Differential	DCLK_A		715
D_AP11	A18	Input	LVCMOS	DDR	Differential	DCLK_A		732
D_AN13	A20	Input	LVCMOS	DDR	Differential	DCLK_A		686
D_AP13	B20	Input	LVCMOS	DDR	Differential	DCLK_A		715
D_AN15	B19	Input	LVCMOS	DDR	Differential	DCLK_A		700
D_AP15	A19	Input	LVCMOS	DDR	Differential	DCLK_A		719
D_BN1	K20	Input	LVCMOS	DDR	Differential	DCLK_B	Input data bus B (LVDS)	716
D_BP1	J20	Input	LVCMOS	DDR	Differential	DCLK_B		745
D_BN3	J19	Input	LVCMOS	DDR	Differential	DCLK_B		686
D_BP3	K19	Input	LVCMOS	DDR	Differential	DCLK_B		703
D_BN5	L18	Input	LVCMOS	DDR	Differential	DCLK_B		686
D_BP5	K18	Input	LVCMOS	DDR	Differential	DCLK_B		714
D_BN7	M18	Input	LVCMOS	DDR	Differential	DCLK_B		693
D_BP7	N18	Input	LVCMOS	DDR	Differential	DCLK_B		709
D_BN9	P20	Input	LVCMOS	DDR	Differential	DCLK_B		687
D_BP9	N20	Input	LVCMOS	DDR	Differential	DCLK_B		715
D_BN11	R18	Input	LVCMOS	DDR	Differential	DCLK_B		702
D_BP11	T18	Input	LVCMOS	DDR	Differential	DCLK_B		719
D_BN13	T20	Input	LVCMOS	DDR	Differential	DCLK_B		686
D_BP13	R20	Input	LVCMOS	DDR	Differential	DCLK_B		715
D_BN15	R19	Input	LVCMOS	DDR	Differential	DCLK_B		680
D_BP15	T19	Input	LVCMOS	DDR	Differential	DCLK_B		700
DCLK_AN	D19	Input	LVCMOS	—	Differential	—	Input data bus A Clock (LVDS)	700
DCLK_AP	E19	Input	LVCMOS	—	Differential	—	Input data bus A Clock (LVDS)	728
DCLK_BN	N19	Input	LVCMOS	—	Differential	—	Input data bus B Clock (LVDS)	700
DCLK_BP	M19	Input	LVCMOS	—	Differential	—	Input data bus B Clock (LVDS)	728
DATA CONTROL INPUTS
SCTRL_AN	F20	Input	LVCMOS	DDR	Differential	DCLK_A	Data Control (LVDS)	716
SCTRL_AP	E20	Input	LVCMOS	DDR	Differential	DCLK_A		731
SCTRL_BN	L20	Input	LVCMOS	DDR	Differential	DCLK_B		707
SCTRL_BP	M20	Input	LVCMOS	DDR	Differential	DCLK_B		722
SERIAL COMMUNICATION (SCP) AND CONFIGURATION
SCP_CLK	A8	Input	LVCMOS	—	Pulldown	—		—
SCP_DO	A9	Output	LVCMOS	—	—	SCP_CLK		—
SCP_DI	A5	Input	LVCMOS	—	Pulldown	SCP_CLK		—
SCP_EN	B7	Input	LVCMOS	—	Pulldown	SCP_CLK		—
PWRDN	B9	Input	LVCMOS	—	Pulldown	—		—
MICROMIRROR BIAS CLOCKING PULSE
MODE_A	A4	Input	LVCMOS	—	Pulldown	—		—
MBRST0	C3	Input	Analog	—	—	—	Micromirror Bias Clocking Pulse "MBRST" signals "clock" micromirrors into state of LVCMOS memory cell associated with each mirror.	—
MBRST1	D2	Input	Analog	—	—	—		—
MBRST2	D3	Input	Analog	—	—	—		—
MBRST3	E2	Input	Analog	—	—	—		—
MBRST4	G3	Input	Analog	—	—	—		—
MBRST5	E1	Input	Analog	—	—	—		—
MBRST6	G2	Input	Analog	—	—	—		—
MBRST7	G1	Input	Analog	—	—	—		—
MBRST8	N3	Input	Analog	—	—	—		—
MBRST9	M2	Input	Analog	—	—	—		—
MBRST10	M3	Input	Analog	—	—	—		—
MBRST11	L2	Input	Analog	—	—	—		—
MBRST12	J3	Input	Analog	—	—	—		—
MBRST13	L1	Input	Analog	—	—	—		—
MBRST14	J2	Input	Analog	—	—	—		—
MBRST15	J1	Input	Analog	—	—	—		—
POWER
V_CC	B11,B12,B13,B16,R12,R13,R16,R17	Power	Analog	—	—	—	Power for LVCMOS Logic	—
V_CCI	A12,A14,A16,T12,T14,T16	Power	Analog	—	—	—	Power supply for LVDS Interface	—
V_CC2	C1,D1,M1,N1	Power	Analog	—	—	—	Power for High Voltage CMOS Logic	—
V_SS	A6,A11,A13,A15,A17,B4,B5,B8,B14,B15,B17,C2,C18,C19,F1,F2,F19,H1,H2,H3,H18,J18,K1,K2,L19,N2,P18,P19,R4,R9,R14,R15,T7,T13,T15,T17	Power	Analog	—	—	—	Common return for all power inputs	—
RESERVED SIGNALS (Not for use in system)
RESERVED_R7	R7	Input	LVCMOS	—	Pulldown	—	Pins should be connected to V_SS	—
RESERVED_R8	R8	Input	LVCMOS	—	Pulldown	—		—
RESERVED_T8	T8	Input	LVCMOS	—	Pulldown	—		—
RESERVED_B6	B6	Input	LVCMOS	—	Pulldown	—		—
NO_CONNECT	A3, A7, A10, B2, B3, B10, E3, F3, K3, L3, P1, P2, P3, R1, R2, R3, R5, R6, R10, R11, T1, T2, T3, T4, T5, T6, T9, T10, T11	—	—	—	—	—	DO NOT CONNECT	—

(1) The following power supplies are required to operate the DMD: VCC, VCCI, VCC2. VSS must also be connected.

(2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to the Section 6.7 for specifications and relationships.

(3) Refer to Section 6.6 for differential termination specification.

(4) Internal Trace Length (mils) refers to the package electrical trace length.