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  • 具有过流保护功能的 LMG341xR050 600V 50mΩ 集成式 GaN 功率级

    • ZHCSIU1A September   2018  – March 2019 LMG3410R050 , LMG3411R050

      ADVANCE INFORMATION for pre-production products; subject to change without notice.  

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  • 具有过流保护功能的 LMG341xR050 600V 50mΩ 集成式 GaN 功率级
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化方框图
      2.      高于 100V/ns 时的开关性能
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Switching Parameters
      1. 7.1.1 Turn-on Delays
      2. 7.1.2 Turn-off Delays
      3. 7.1.3 Drain Slew Rate
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Direct-Drive GaN Architecture
      2. 8.3.2 Internal Buck-Boost DC-DC Converter
      3. 8.3.3 Internal Auxiliary LDO
      4. 8.3.4 Fault Detection
        1. 8.3.4.1 Over-current Protection
        2. 8.3.4.2 Over-Temperature Protection and UVLO
      5. 8.3.5 Drive Strength Adjustment
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Slew Rate Selection
          1. 9.2.2.1.1 Startup and Slew Rate with Bootstrap High-Side Supply
        2. 9.2.2.2 Signal Level-Shifting
        3. 9.2.2.3 Buck-Boost Converter Design
      3. 9.2.3 Application Curves
    3. 9.3 Paralleling GaN Devices
    4. 9.4 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Using an Isolated Power Supply
    2. 10.2 Using a Bootstrap Diode
      1. 10.2.1 Diode Selection
      2. 10.2.2 Managing the Bootstrap Voltage
      3. 10.2.3 Reliable Bootstrap Start-up
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Loop Inductance
      2. 11.1.2 Signal Ground Connection
      3. 11.1.3 Bypass Capacitors
      4. 11.1.4 Switch-Node Capacitance
      5. 11.1.5 Signal Integrity
      6. 11.1.6 High-Voltage Spacing
      7. 11.1.7 Thermal Recommendations
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

具有过流保护功能的 LMG341xR050 600V 50mΩ 集成式 GaN 功率级

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • TI GaN 工艺通过了实际应用硬开关任务剖面可靠性加速测试
  • 支持高密度电源转换设计
    • 与共源共栅或独立 GaN FET 相比具有卓越的系统性能
    • 低电感 8mm x 8mm QFN 封装简化了设计和布局
    • 可调节驱动强度确保开关性能和 EMI 控制
    • 数字故障状态输出信号
    • 仅需 +12V 非稳压电源
  • 集成栅极驱动器
    • 零共源电感
    • 20ns 传播延迟，确保 MHz 级工作频率
    • 工艺经过调整的栅极偏置电压，确保可靠性
    • 25V/ns 至 100V/ns 的用户可调节压摆率
  • 强大的保护
    • 无需外部保护组件
    • 过流保护，响应时间低于 100ns
    • 压摆率抗扰性高于 150V/ns
    • 瞬态过压抗扰度
    • 过热保护
    • 针对所有电源轨的 UVLO 保护
  • 强大的保护
    • LMG3410R050：锁存过流保护
    • LMG3411R050：逐周期过流保护

    2 应用

    • 高密度工业电源和消费类电源
    • 多电平转换器
    • 光伏逆变器
    • 工业电机驱动
    • 不间断电源
    • 高电压电池充电器

    3 说明

    LMG341xR050 GaN 功率级具有集成驱动器和保护功能，可让设计人员在电力电子系统中实现更高水平的功率密度和效率。LMG341x 的固有优势超越硅 MOSFET，包括超低输入和输出电容值、可将开关损耗降低 80% 的零反向恢复以及可降低 EMI 的低开关节点振铃。这些优势支持诸如图腾柱 PFC 之类的密集高效拓扑。

    LMG341xR050 通过集成一系列独一无二的 特性 提供了传统共源共栅 GaN 和独立 GaN FET 的智能替代产品，以简化设计、最大限度地提高可靠性并优化任何电源的性能。集成式栅极驱动器支持 100V/ns 开关（Vds 振铃几乎为零），低于 100ns 的限流可自行防止意外击穿事件，过热关断可防止热逃逸，而且系统接口信号可提供自监控功能。

    器件信息(1)

    器件型号 封装 封装尺寸（标称值）
    LMG341xR050 QFN (32) 8.00mm x 8.00mm
    1. 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

    Device Images

    简化方框图

    LMG3410R050 LMG3411R050 LMG3410R070-simplified-block-diagram-SNOSD10.gif

    高于 100V/ns 时的开关性能

    LMG3410R050 LMG3411R050 waveform-01-GaN-PowerStage-snosd10.png

    4 修订历史记录

    Changes from * Revision (September 2018) to A Revision

    • Added LMG3411R050 器件Go

    5 Pin Configuration and Functions

    RWH (QFN) PACKAGE
    32 PINS
    (Top View)
    LMG3410R050 LMG3411R050 pin_diagram_snosd10.gif

    Pin Functions

    PIN I/O(1) DESCRIPTION
    NAME NO.
    BBSW 28 P Internal buck-boost converter switch pin. Connect an inductor from this point to source
    DRAIN 1-11 P Power transistor drain
    FAULT 32 O Fault output, push-pull, active low
    IN 31 I CMOS-compatible non-inverting gate drive input
    LDO5V 25 P 5-V LDO output for external digital isolator.
    LPM 29 I Enables low-power-mode by connecting the pin to source
    SOURCE 12-16, 18-24 P Power transistor source, die-attach pad, thermal sink, signal ground reference
    RDRV 30 I Drive strength selection pin. Connect a resistor from this pin to ground to set the turn-on drive strength to control slew rate,
    VDD 27 P 12-V power input, relative to source. Supplies 5-V rail and gate drive supply.
    VNEG 26 P Negative supply output, bypass to source with 2.2-µF capacitor
    NC 17 — Not connected, connect to source or leave floating.
    PAD — P Thermal Pad, tie to source with multiple vias.
    (1) I = Input, O = Output, P = Power

    6 Specifications

    6.1 Absolute Maximum Ratings

    over operating free-air temperature range (unless otherwise noted) (1)
    MIN MAX UNIT
    V DS Drain-Source Voltage 600 V
    VDS(TR)(2) Transient Drain-Source Voltage 800 V
    V DD Supply Voltage –0.3 20 V
    I DS,pul(3) Drain-Source Current, Pulsed 130 A
    V IN IN, LPM Pin Voltage -0.3 5.5 V
    V FAULT FAULT Pin Voltage –0.3 5.5 V
    T STG Storage Temperature –55 150 °C
    T J Operating Temperature –40 150 °C
    (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
    (2) <1% duty cycle, <1us, for 1M pulses
    (3) Pulse current <100ns

    6.2 ESD Ratings

    VALUE UNIT
    V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±1000 V
    Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±250
    (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
    (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

     
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