ZHCSIH9F March 2009 – July 2018 TPS65023-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CORE4 | CORE3 | CORE2 | CORE1 | CORE0 | |||
R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-DEFDCDC1 | R/W-DEFDCDC1 | R/W-DEFDCDC1 | R/W-DEFDCDC1 |
RESET(1): DEFCORE is reset to its default value by one of these events:
Bit | Field | Type | Reset | Description | |
---|---|---|---|---|---|
4–0 | CORE4, CORE3, CORE2, CORE1,CORE0 | R/W | 10100 |
These bits set VDCDC1. 00000 = 0.8 V 00001 = 0.825 V 00010 = 0.85 V 00011 = 0.875 V 00100 = 0.9 V 00101 = 0.925 V 00110 = 0.95 V 00111 = 0.975 V 01000 = 1 V 01001 = 1.025 V 01010 = 1.05 V 01011 = 1.075 V 01100 = 1.1 V 01101 = 1.125 V 01110 = 1.15 V 01111 = 1.175 V |
10000 = 1.2 V 10001 = 1.225 V 10010 = 1.25 V 10011 = 1.275 V 10100 = 1.3 V 10101 = 1.325 V 10110 = 1.35 V 10111 = 1.375 V 11000 = 1.4 V 11001 = 1.425 V 11010 = 1.45 V 11011 = 1.475 V 11100 = 1.5 V 11101 = 1.525 V 11110 = 1.55 V 11111 = 1.6 V |