ZHCSIH9F March 2009 – July 2018 TPS65023-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GO | Core adj allowed | DCDC2 discharge | DCDC1 discharge | DCDC3 discharge | |||
R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
The CON_CTRL2 register can be used to take control the inductive converters.
RESET(1): CON_CTRL2[6] is reset to its default value by one of these events:
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | GO | R/W | 0 |
0 = no change in the output voltage for the DCDC1 converter 1 = the output voltage of the DCDC1 converter is changed to the value defined in DEFCORE with the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is complete. The transition is considered complete in this case when the desired output voltage code has been reached, not when the VDCDC3 output voltage is actually in regulation at the desired voltage. |
6 | CORE ADJ allowed | R/W | 1 |
0 = the output voltage is set with the I2C register 1 = DEFDCDC1 is either connected to GND or VCC or an external voltage divider. When connected to GND or VCC, VDCDC1 defaults to 1.2 V or 1.6 V, respectively, at start-up. |
2–0 | DCDC2, DCDC1, DCDC3 discharge | R/W | 000 |
0 = the output capacitor of the associated converter is not actively discharged when the converter is disabled. 1 = the output capacitor of the associated converter is actively discharged when the converter is disabled. This decreases the fall time of the output voltage at light load. |