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  • 具有 3 个直流/直流转换器、3 个 LDO、I2C 接口和 DVS 的 TPS65023-Q1 电源管理 IC (PMIC)

    • ZHCSIH9F March   2009  – July 2018 TPS65023-Q1

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  • 具有 3 个直流/直流转换器、3 个 LDO、I2C 接口和 DVS 的 TPS65023-Q1 电源管理 IC (PMIC)
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      2. 8.3.2 Soft Start
      3. 8.3.3 Active Discharge When Disabled
      4. 8.3.4 Power-Good Monitoring
      5. 8.3.5 Low-Dropout Voltage Regulators
      6. 8.3.6 Undervoltage Lockout
    4. 8.4 Device Functional Modes
      1. 8.4.1 VRTC Output and Operation With or Without Backup Battery
      2. 8.4.2 Power-Save Mode Operation (PSM)
      3. 8.4.3 Low-Ripple Mode
      4. 8.4.4 100% Duty-Cycle Low-Dropout Operation
      5. 8.4.5 System Reset and Control Signals
        1. 8.4.5.1 DEFLDO1 and DEFLDO2
        2. 8.4.5.2 Interrupt Management and the INT Pin
    5. 8.5 Programming
      1. 8.5.1 Power-Up Sequencing
      2. 8.5.2 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 VERSION Register (address: 00h) Read-Only
      2. 8.6.2 PGOODZ Register (address: 01h) Read-Only
        1. Table 5. PGOODZ Register Field Descriptions
      3. 8.6.3 MASK Register (address: 02h)
      4. 8.6.4 REG_CTRL Register (address: 03h)
        1. Table 6. REG_CTRL Register Field Descriptions
      5. 8.6.5 CON_CTRL Register (address: 04h)
        1. Table 7. CON_CTRL Register Field Descriptions
      6. 8.6.6 CON_CTRL2 Register (address: 05h)
        1. Table 8. CON_CTRL2 Register Field Descriptions
      7. 8.6.7 DEFCORE Register (address: 06h)
        1. Table 9. DEFCORE Register Field Descriptions
      8. 8.6.8 DEFSLEW Register (address: 07h)
        1. Table 10. DEFSLEW Register Field Descriptions
      9. 8.6.9 LDO_CTRL Register (address: 08h)
        1. Table 11. LDO_CTRL Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reset Condition of DCDC1
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection for the DC-DC Converters
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Voltage Selection
        5. 9.2.2.5 VRTC Output
        6. 9.2.2.6 LDO1 and LDO2
        7. 9.2.2.7 TRESPWRON
        8. 9.2.2.8 VCC Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

具有 3 个直流/直流转换器、3 个 LDO、I2C 接口和 DVS 的 TPS65023-Q1 电源管理 IC (PMIC)

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 符合汽车类应用的 要求
  • 具有符合 AEC-Q100 标准的下列结果：
    • 器件温度 1 级：–40°C 至 125°C 的环境工作温度范围
    • 器件 HBM ESD 分类等级 2
    • 器件 CDM ESD 分类等级 C4A（RHA 封装）或 C5（RSB 封装）
  • 用于处理器内核的高效 (90%) 1.5A 降压转换器 (VDCDC1)
  • 用于系统电压的高效 (95%) 1.2A 降压转换器 (VDCDC2)
  • 用于存储器电压的高效 (92%) 1A 降压转换器 (VDCDC3)
  • 用于支持实时时钟 (VRTC) 的 30mA LDO/开关
  • 2 × 200mA 通用低压降 LDO (LDO)
  • 用于处理器内核的动态电压管理
  • 可使用两个数字输入引脚进行 LDO 电压预选
  • 外部可调复位延迟时间
  • 电池备用功能
  • 用于电感转换器的单独使能引脚
  • 兼容 I2C 的串行接口
  • 85μA 静态电流
  • 低纹波脉冲频率调制 (PFM) 模式
  • 热关断保护

2 应用

  • 汽车仪表组
  • 汽车信息娱乐系统
  • 数字音频广播
  • 电源 DaVinci™数字信号处理器 (DSP) 系列解决方案

3 说明

TPS65023-Q1 器件是一款集成式电源管理集成电路 (IC)，适用于 由锂离子或锂聚合物电池供电的 应用（此类应用需要使用多条电源轨）。TPS65023-Q1 器件具有三个高效的降压转换器，可在基于处理器的系统内提供内核电压、外设、输入和输出 (I/O) 以及存储器电源轨。内核转换器可通过串行接口实现动态电压变化，从而使系统实现动态节能。这三个降压转换器会在轻负载时进入低功耗模式，从而在可能的最宽负载电流范围内实现最高效率。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TPS65023-Q1 VQFN (40) 6.00mm × 6.00mm
WQFN (40) 5.00mm × 5.00mm
  1. 要了解所有可用封装，请见产品说明书末尾的可订购产品附录。

Device Images

简化原理图

TPS65023-Q1 Keygraphic.gif

4 修订历史记录

Changes from E Revision (March 2016) to F Revision

  • Changed 产品说明书的标题Go
  • Changed all references of PowerPAD to thermal padGo
  • Changed the units of the current and peak current parameters from V to mA in the Absolute Maximum Ratings tableGo
  • Added 接收文档更新通知 部分Go

Changes from D Revision (September 2011) to E Revision

  • Added 器件信息 表、目录、修订历史记录 部分、引脚配置和功能 部分、规格 部分、ESD 额定值 表、详细 说明部分，应用和实施部分，电源相关建议部分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分Go
  • Changed maximum junction temperature from 125°C to 150°CGo

5 说明 （续）

TPS65023-Q1 器件还集成了两个可通过外部输入引脚启用的通用 200mA LDO 稳压器。每个 LDO 可在 1.5V 至 6.5V 输入电压范围内正常运行，这使得它们可以由其中一个降压转换器供电，也可以由主电池直接供电。用户可使用 DEFLDO1 和 DEFLDO2 引脚通过数字方式将这两个 LDO 的默认输出电压设置为四个不同的电压组合。串行电压可用于动态电压调节和屏蔽中断，或用于停用、启用和设置 LDO 输出电压。该接口符合快速模式或标准模式 I2C 规格，可实现 400kHz 的传输频率。TPS65023-Q1 器件在自然通风环境下的额定运行温度范围为 –40°C 至 125°C。

6 Pin Configuration and Functions

RHA and RSB Packages
40-Pin VQFN and WQFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
SWITCHING REGULATOR
AGND1 40 — Analog ground. All analog ground pins are connected internally on the chip
AGND2 17 — Analog ground. All analog ground pins are connected internally on the chip
DCDC1_EN 25 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator
DCDC2_EN 24 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator
DCDC3_EN 23 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator
DEFDCDC1 10 I Input for signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V. DEFDCDC1 can also be connected to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V.
DEFDCDC2 32 I Input for signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V. DEFDCDC2 can also be connected to a resistor divider between VDCDC2 and GND, if the output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V.
DEFDCDC3 1 I Input for signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V. DEFDCDC3 can also be connected to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V.
L1 7 — Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
L2 35 — Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here
L3 4 — Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here
PGND1 8 — Power ground for VDCDC1 converter
PGND2 34 — Power ground for VDCDC2 converter
PGND3 3 — Power ground for VDCDC3 converter
VCC 37 I Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 DC-DC converters. VCC must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. VCC also supplies serial interface block.
VDCDC1 9 I VDCDC1 feedback voltage sense input. Connect directly to VDCDC1
VDCDC2 33 I VDCDC2 feedback voltage sense input. Connect directly to VDCDC2
VDCDC3 2 I VDCDC3 feedback voltage sense input. Connect directly to VDCDC3
VINDCDC1 6 I Input for VDCDC1 step-down converter. VINDCDC1 must be connected to the same voltage supply as VINDCDC2, VINDCDC3, and VCC
VINDCDC2 36 I Input for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage supply as VINDCDC1, VINDCDC3, and VCC
VINDCDC3 5 I Input for VDCDC3 step-down converter. VINDCDC3 must be connected to the same voltage supply as VINDCDC1, VINDCDC2, and VCC
Thermal pad — — Connect the thermal pad to analog ground
LDO REGULATOR
DEFLD01 12 I Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2
DEFLD02 13 I Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2
LDO_EN 22 I Enable input for LDO1 and LDO2. A logic high enables the LDOs, a logic low disables the LDOs
VBACKUP 15 I Connect the backup battery to this input pin
VINLDO 19 I Input for LDO1 and LDO2
VLDO1 20 O Output of LDO1
VLDO2 18 O Output of LDO2
VRTC 16 O Output of the LDO/switch for the real time clock
VSYSIN 14 I Input of system voltage for VRTC switch
CONTROL AND I2C
HOT_RESET 11 I Push-button input that reboots or wakes up the processor through RESPWRON output pin
INT 28 O Open drain output
LOW_BAT 21 O Open-drain output of LOW_BAT comparator
LOWBAT_SNS 39 I Input for the comparator driving the LOW_BAT output
PWRFAIL 31 O Open-drain output. Active low when PWRFAIL comparator indicates low VBAT condition
PWRFAIL_SNS 38 I Input for the comparator driving the PWRFAIL output
RESPWRON 27 O Open-drain system reset output
SCLK 30 I Serial interface clock line
SDAT 29 I/O Serial interface data/address
TRESPWRON 26 I Connect the timing capacitor to TRESPWRON to set the reset delay time: 1 nF → 100 ms.

7 Specifications

 
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