ZHCSHU4E April   2005  – March 2018 DAC7811

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      框图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics: VDD = 5 V
    7. 6.7 Typical Characteristics: VDD = 2.7 V
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
      2. 7.4.2 Input Shift Register
      3. 7.4.3 SYNC Interrupt (Stand-Alone Mode)
      4. 7.4.4 Daisy-Chain
      5. 7.4.5 Control Bits C3 to C0
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Unipolar Operation Using DAC7811
      2. 8.1.2 Bipolar Operation Using the DAC7811
      3. 8.1.3 Stability Circuit
      4. 8.1.4 Amplifier Selection
      5. 8.1.5 Programmable Current Source Circuit
    2. 8.2 Typical Application
      1. 8.2.1 Single Supply Unipolar Multiplying DAC
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

Control Bits C3 to C0

Control Bits C3 to C0 allow control of various functions of the DAC; see Table 3. Default settings of the DAC on powering up are as follows: Data clocked into shift register on falling clock edges; daisy-chain mode is enabled. The device powers on with zero-scale loaded into the DAC register and IOUT lines. The DAC control bits allow the user to adjust certain features as part of an initialization sequence; for example, daisy-chaining may be disabled if not in use, active clock edge may be changed to rising edge, and DAC output may be cleared to either zero or midscale. The user may also initiate a readback of the DAC register contents for verification purposes.

Table 3. Serial Input Register Data Format, Data Loaded MSB First

C3 C2 C1 C0 FUNCTION IMPLEMENTED
0 0 0 0 No operation (power-on default)
0 0 0 1 Load and update
0 0 1 0 Initiate readback
0 0 1 1 Reserved
0 1 0 0 Reserved
0 1 0 1 Reserved
0 1 1 0 Reserved
0 1 1 1 Reserved
1 0 0 0 Reserved
1 0 0 1 Daisy-chain disable
1 0 1 0 Clock data to shift register on rising edge
1 0 1 1 Clear DAC output to zero
1 1 0 0 Clear DAC output to midscale
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved