DATA SHEET
DAC7811 12 位串行输入乘法数模转换器
本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。
1 特性
- 2.7V 至 5.5V 电源供电
- 50MHz串口
- 10MHz 的乘法带宽
- ±15V 基准输入
- 低毛刺脉冲能量：5 nV-s
- 工作温度范围：
-40°C 至 +125°C - 10 引脚超薄小外形尺寸 (VSSOP) 封装
- 12 位单调性
- 四象限乘法
- 上电复位（具有欠压保护功能）
- 菊链模式
- 读回功能
- 工业标准引脚配置
2 应用
- 便携式电池供电仪表
- 波形发生器
- 模拟处理
- 可编程放大器和衰减器
- 数控校准
- 可编程滤波器和振荡器
- 复合视频
- 超声波
3 说明
DAC7811 是一款 CMOS 12 位电流输出数模转换器 (DAC)。该器件由 2.7V 至 5.5V 电源供电，这使得该器件非常适合电池供电的应用和许多其他 应用。
该 DAC 使用与 SPI、 QSPI™、MICROWIRE 和大多数 DSP 接口标准相兼容的双缓冲 3 线串行接口。此外，在使用多个器件时，可以通过串行数据输出引脚 (SDO) 实现菊链。利用数据读回功能，用户可以通过 SDO 引脚读取 DAC 寄存器的内容。一旦加电，内部移位寄存器和锁存器中就会填充零，并且 DAC 输出将处于零标度。
DAC7811 可提供出色的四象限乘法特性以及 10MHz 的大信号乘法带宽。施加的外部基准输入电压 (VREF) 确定满标量程输出电流。与外部电流到电压精密放大器结合使用时，集成式反馈电阻器 (RFB) 可提供温度跟踪和满标量程电压输出。
DAC7811 采用 10 引线 VSSOP 封装。
器件信息(1)
| 器件型号 | 封装 | 封装尺寸（标称值） |
|---|---|---|
| DAC7811 | VSSOP (10) | 3.00mm x 3.00mm |
- 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
Device Images
框图
5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | IOUT1 | O | DAC Current Output |
| 2 | IOUT2 | O | DAC Analog Ground. This pin is normally tied to the analog ground of the system. |
| 3 | GND | G | Ground pin. |
| 4 | SCLK | I | Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift register on the rising edge of SCLK. |
| 5 | SDIN | I | Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to the rising edge. |
| 6 | SYNC | I | Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on the active edge of the following clocks (power-on default is falling clock edge). In stand-alone mode, the serial interface counts the clocks and data is latched to the shift register on the 16th active clock edge. |
| 7 | SDO | O | Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift register on the falling edge and out via SDO on the rising edge of SCLK. Data will always be clocked out on the alternate edge to loading data to the shift register. Writing the Readback control word to the shift register makes the DAC register contents available for readback on the SDO pin, clocked out on the opposite edges to the active clock edge. |
| 8 | VDD | I | Positive Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V. |
| 9 | VREF | I | DAC Reference Voltage Input |
| 10 | RFB | O | DAC Feedback Resistor pin. Establish voltage output for the DAC by connecting to external amplifier output. |
