| 00h |
MONOSHOT_BIT |
FORCE_EN_SLAVE |
FORCE_EN_BYPASS |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
I2C_CONT_RW |
0 |
0 |
0 |
0 |
0 |
SOFTWARE_RESET |
| 01h |
0 |
0 |
I2C_RW |
I2C_EN |
I2C_TRIG_REG |
FRAME_VD_TRIG |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
ADDR_SLAVE_EEPROM |
SWAP_READ_DATA |
EEPROM_READ_TRIG |
| 02h |
TEMP_AVG_ILLUM |
EN_TILLUM_READ |
TSENS_SLAVE2 |
TSENS_SLAVE1 |
TSENS_SLAVE0 |
| 03h |
TEMP_AVG_MAIN |
0 |
0 |
0 |
0 |
I2C_NUM_TRAN |
I2C_WRITE_DATA1 |
INIT_LOAD_DONE |
I2C_READ_DATA |
| 04h |
TILLUM_UNSIGNED |
0 |
0 |
0 |
TILLUM |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
| 05h |
I2C_NUM_BYTES_TRAN2 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| 07h |
CONFIG_TILLUM_MSB |
I2C_SEL_READ_BYTES |
I2C_NUM_BYTES_TRAN1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
I2C_WRITE_DATA2 |
| 08h |
FRAME_COUNT0 |
AMB_OVL_FLAG |
MOD_FREQ |
FRAME_STATUS |
TX_CHANNEL |
HDR_MODE |
PHASE_OVER_FLOW |
PHASE_OUT |
| 09h |
DEALIAS_BIN |
PHASE_OVER_FLOW_F2 |
SIG_OVL_FLAG |
FRAME_COUNT1 |
AMP_OUT |
| 0Ah |
TMAIN |
AMB_DATA |
FRAME_COUNT2 |
| 0Bh |
AMB_CALIB |
DIG_GPO_SEL2 |
0 |
0 |
DIG_GPO_SEL1 |
DIG_GPO_SEL0 |
| 0Ch |
AMB_PHASE_CORR_PWL_COEFF0 |
AMB_XTALK_QPHASE_COEFF |
AMB_XTALK_IPHASE_COEFF |
| 0Dh |
EN_TILLUM_12B |
0 |
0 |
0 |
0 |
0 |
0 |
AMB_SAT_THR |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| 0Fh |
EN_FREQ_CORR |
EN_FLOOP |
EN_AUTO_FREQ_COUNT |
SYS_CLK_DIVIDER |
START_FREQ_CALIB |
0 |
REF_COUNT_LIMIT |
| 10h |
AMPLITUDE_MIN_THR[15:8] |
EN_CONT_FCALIB |
FREQ_COUNT_READ_REG |
| 11h |
AMPLITUDE_MIN_THR[7:0] |
DIS_OVL_GATING |
FREQ_COUNT_REG |
| 13h |
0 |
0 |
0 |
0 |
0 |
COMPARE_REG1 |
MUX_SEL_COMPIN |
| 14h |
0 |
0 |
0 |
0 |
DIS_INTERRUPT |
STATUS_IN_REG |
EN_PROCESSOR_VALUES |
EN_SEQUENCER |
COMPARE_REG2 |
| 15h |
COMMAND1 |
COMMAND0 |
| 16h |
COMMAND3 |
COMMAND2 |
| 17h |
COMMAND5 |
COMMAND4 |
| 18h |
COMMAND7 |
COMMAND6 |
| 19h |
COMMAND9 |
COMMAND8 |
| 1Ah |
COMMAND11 |
COMMAND10 |
| 1Bh |
COMMAND13 |
COMMAND12 |
| 1Ch |
COMMAND15 |
COMMAND14 |
| 1Dh |
COMMAND17 |
COMMAND16 |
| 1Eh |
COMMAND19 |
COMMAND18 |
| 26h |
POWERUP_DELAY |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
| 27h |
MONOSHOT_FZ_CLKCNT |
MONOSHOT_NUMFRAME |
MONOSHOT_MODE |
| 29h |
ILLUM_DAC_L_TX2[4:1] |
ILLUM_DAC_H_TX1 |
ILLUM_DAC_L_TX1 |
ILLUM_DAC_H_TX0 |
ILLUM_DAC_L_TX0 |
| 2Ah |
ILLUM_DAC_L_TX2[0] |
ILLUM_DAC_H_TX2 |
0 |
SEL_HDR_MODE |
EN_ADAPTIVE_HDR |
TX_SEQ_REG |
SEL_TX_CH |
EN_TX_SWITCH |
| 2Bh |
0 |
0 |
ILLUM_SCALE_H_TX0 |
ILLUM_SCALE_L_TX0 |
HDR_THR_HIGH |
| 2Ch |
0 |
0 |
ILLUM_SCALE_H_TX1 |
ILLUM_SCALE_L_TX1 |
HDR_THR_LOW |
| 2Dh |
TEMP_COEFF_MAIN_HDR0_TX1 |
TEMP_COEFF_MAIN_HDR1_TX0 |
| 2Eh |
XTALK_FILT_TIME_CONST |
ILLUM_XTALK_REG_SCALE |
INT_XTALK_REG_SCALE |
0 |
ILLUM_XTALK_CALIB |
IQ_READ_DATA_SEL |
USE_XTALK_REG_ILLUM |
USE_XTALK_FILT_ILLUM |
USE_XTALK_REG_INT |
USE_XTALK_FILT_INT |
INT_XTALK_CALIB |
DIS_AUTO_SCALE |
FORCE_SCALE_VAL |
| 2Fh |
TEMP_COEFF_MAIN_HDR1_TX1[11:4] |
IPHASE_XTALK_REG_HDR0_TX0 |
| 30h |
TEMP_COEFF_MAIN_HDR1_TX1[3:0] |
0 |
0 |
0 |
0 |
QPHASE_XTALK_REG_HDR0_TX0 |
| 31h |
TEMP_COEFF_MAIN_HDR0_TX2[11:4] |
IPHASE_XTALK_REG_HDR1_TX0 |
| 32h |
TEMP_COEFF_MAIN_HDR0_TX2[3:0] |
0 |
0 |
0 |
0 |
QPHASE_XTALK_REG_HDR1_TX0 |
| 33h |
TEMP_COEFF_MAIN_HDR1_TX2[11:4] |
IPHASE_XTALK_REG_HDR0_TX1 |
| 34h |
TEMP_COEFF_MAIN_HDR1_TX2[3:0] |
0 |
0 |
0 |
0 |
QPHASE_XTALK_REG_HDR0_TX1 |
| 35h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
IPHASE_XTALK_REG_HDR1_TX1 |
| 36h |
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR0_TX0 |
QPHASE_XTALK_REG_HDR1_TX1 |
| 37h |
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR0_TX0 |
IPHASE_XTALK_REG_HDR0_TX2 |
| 38h |
TEMP_COEFF_XTALK_IPHASE_HDR0_TX0 |
QPHASE_XTALK_REG_HDR0_TX2 |
| 39h |
TEMP_COEFF_XTALK_QPHASE_HDR0_TX0 |
IPHASE_XTALK_REG_HDR1_TX2 |
| 3Ah |
0 |
SCALE_AMB_COEFF_XTALK |
SCALE_TEMP_COEFF_XTALK |
EN_TEMP_XTALK_CORR |
QPHASE_XTALK_REG_HDR1_TX2 |
| 3Bh |
IPHASE_XTALK |
| 3Ch |
QPHASE_XTALK |
| 3Dh |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
IPHASE_XTALK_INT_REG |
| 3Eh |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
QPHASE_XTALK_INT_REG |
| 3Fh |
TILLUM_CALIB_HDR0_TX2 |
TMAIN_CALIB_HDR0_TX2 |
| 40h |
0 |
EN_MULTI_FREQ_PHASE |
NCR_CONFIG |
BETA0_DEALIAS_SCALE |
ALPHA0_DEALIAS_SCALE |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
EN_DEALIAS_MEAS |
| 41h |
TMAIN_CALIB_HDR1_TX1 |
BETA1_DEALIAS_SCALE |
ALPHA1_DEALIAS_SCALE |
| 42h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
PHASE_OFFSET_HDR0_TX0 |
| 43h |
TILLUM_CALIB_HDR1_TX1 |
0 |
0 |
0 |
SCALE_PHASE_TEMP_COEFF |
0 |
0 |
0 |
0 |
EN_TEMP_CORR |
EN_PHASE_CORR |
| 44h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
PHASE2_OFFSET_HDR0_TX0 |
| 45h |
TMAIN_CALIB_HDR1_TX2 |
TEMP_COEFF_MAIN_HDR0_TX0 |
| 46h |
TILLUM_CALIB_HDR1_TX2 |
TEMP_COEFF_ILLUM_HDR0_TX0 |
| 47h |
TILLUM_CALIB_HDR0_TX0 |
TMAIN_CALIB_HDR0_TX0 |
| 48h |
TILLUM_CALIB_HDR1_TX0 |
TMAIN_CALIB_HDR1_TX0 |
| 49h |
TILLUM_CALIB_HDR0_TX1 |
TMAIN_CALIB_HDR0_TX1 |
| 4Ah |
0 |
0 |
0 |
0 |
SCALE_NL_CORR_COEFF |
A0_COEFF_HDR0_TX0 |
0 |
EN_NL_CORR |
| 4Bh |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
A1_COEFF_HDR0_TX0 |
| 4Ch |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
A2_COEFF_HDR0_TX0 |
| 4Dh |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
A3_COEFF_HDR0_TX0 |
| 4Eh |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
A4_COEFF_HDR0_TX0 |
| 50h |
0 |
OVERRIDE_CLKGEN_REG |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
CLIP_MODE_OFFSET |
CLIP_MODE_TEMP |
CLIP_MODE_NL |
CLIP_MODE_FC |
| 51h |
TEMP_COEFF_ILLUM_HDR1_TX0[11:4] |
PHASE_OFFSET_HDR1_TX0 |
| 52h |
TEMP_COEFF_ILLUM_HDR1_TX0[3:0] |
0 |
0 |
0 |
0 |
PHASE_OFFSET_HDR0_TX1 |
| 53h |
TEMP_COEFF_ILLUM_HDR0_TX1[11:4] |
PHASE_OFFSET_HDR1_TX1 |
| 54h |
TEMP_COEFF_ILLUM_HDR0_TX1[3:0] |
0 |
0 |
0 |
0 |
PHASE_OFFSET_HDR0_TX2 |
| 55h |
TEMP_COEFF_ILLUM_HDR1_TX1[11:4] |
PHASE_OFFSET_HDR1_TX2 |
| 56h |
TEMP_COEFF_ILLUM_HDR1_TX1[3:0] |
0 |
0 |
0 |
0 |
PHASE2_OFFSET_HDR1_TX0 |
| 57h |
TEMP_COEFF_ILLUM_HDR0_TX2[11:4] |
PHASE2_OFFSET_HDR0_TX1 |
| 58h |
TEMP_COEFF_ILLUM_HDR0_TX2[3:0] |
0 |
0 |
0 |
0 |
PHASE2_OFFSET_HDR1_TX1 |
| 59h |
TEMP_COEFF_ILLUM_HDR1_TX2[11:4] |
PHASE2_OFFSET_HDR0_TX2 |
| 5Ah |
TEMP_COEFF_ILLUM_HDR1_TX2[3:0] |
0 |
0 |
0 |
0 |
PHASE2_OFFSET_HDR1_TX2 |
| 5Bh |
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR1_TX1 |
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR0_TX1 |
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR1_TX0 |
| 5Ch |
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR1_TX0 |
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR1_TX2 |
TEMP_COEFF_ILLUM_XTALK_IPHASE_HDR0_TX2 |
| 5Dh |
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR0_TX2 |
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR1_TX1 |
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR0_TX1 |
| 5Eh |
TEMP_COEFF_XTALK_IPHASE_HDR0_TX1 |
TEMP_COEFF_XTALK_IPHASE_HDR1_TX0 |
TEMP_COEFF_ILLUM_XTALK_QPHASE_HDR1_TX2 |
| 5Fh |
TEMP_COEFF_XTALK_IPHASE_HDR1_TX2 |
TEMP_COEFF_XTALK_IPHASE_HDR0_TX2 |
TEMP_COEFF_XTALK_IPHASE_HDR1_TX1 |
| 60h |
TEMP_COEFF_XTALK_QPHASE_HDR1_TX1 |
TEMP_COEFF_XTALK_QPHASE_HDR0_TX1 |
TEMP_COEFF_XTALK_QPHASE_HDR1_TX0 |
| 61h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TEMP_COEFF_XTALK_QPHASE_HDR1_TX2 |
TEMP_COEFF_XTALK_QPHASE_HDR0_TX2 |
| 64h |
PROG_OVLDET_REFM |
PROG_OVLDET_REFP |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| 65h |
DIS_OVLDET |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| 6Eh |
0 |
0 |
0 |
0 |
EN_TEMP_CONV |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| 71h |
0 |
0 |
0 |
0 |
0 |
0 |
UNMASK_ILLUMEN_INTXTALK |
EN_ILLUM_CLK_GPIO |
ILLUM_CLK_GPIO_MODE |
0 |
0 |
DIS_ILLUM_CLK_TX |
INVERT_AFE_CLK |
0 |
INVERT_TG_CLK |
SHUT_CLOCKS |
0 |
SHIFT_ILLUM_PHASE |
DEALIAS_FREQ |
DEALIAS_EN |
0 |
| 72h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
IAMB_MAX_SEL |
0 |
0 |
0 |
0 |
| 76h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
PDN_GLOBAL |
0 |
DIS_GLB_PD_I2CHOST |
DIS_GLB_PD_OSC |
RESERVED |
DIS_GLB_PD_AMB_ADC |
DIS_GLB_PD_AMB_DAC |
DIS_GLB_PD_AFE_DAC |
DIS_GLB_PD_AFE |
DIS_GLB_PD_ILLUM_DRV |
DIS_GLB_PD_TEMP_SENS |
DIS_GLB_PD_REFSYS |
| 77h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
EN_DYN_PD_I2CHOST_OSC |
EN_DYN_PD_OSC |
RESERVED |
EN_DYN_PD_AMB_ADC |
EN_DYN_PD_AMB_DAC |
EN_DYN_PD_AFE_DAC |
EN_DYN_PD_AFE |
EN_DYN_PD_ILLUM_DRV |
EN_DYN_PD_TEMP_SENS |
EN_DYN_PD_REFSYS |
| 78h |
0 |
SEL_GP3_ON_SDAM |
0 |
0 |
0 |
0 |
0 |
GPIO2_IBUF_EN |
GPIO2_OBUF_EN |
0 |
GPIO1_IBUF_EN |
GPIO1_OBUF_EN |
GPO2_MUX_SEL |
GPO1_MUX_SEL |
0 |
0 |
0 |
GPO3_MUX_SEL |
| 79h |
0 |
0 |
0 |
0 |
PDN_ILLUM_DRV |
0 |
0 |
0 |
0 |
0 |
0 |
PDN_ILLUM_DC_CURR |
ILLUM_DC_CURR_DAC |
0 |
0 |
0 |
EN_TX_DC_CURR_ALL |
SEL_ILLUM_TX0_ON_TX1 |
EN_TX_CLKZ |
0 |
EN_TX_CLKB |
| 7Ah |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TX0_PIN_CONFIG |
TX2_PIN_CONFIG |
TX1_PIN_CONFIG |
| 80h |
DIS_TG_ACONF |
0 |
0 |
0 |
0 |
0 |
0 |
SUB_VD_CLK_CNT |
TG_EN |
| 83h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_AFE_RST_START |
| 84h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_AFE_RST_END |
| 85h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_SEQ_INT_START |
| 86h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_SEQ_INT_END |
| 87h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_CAPTURE_START |
| 88h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_CAPTURE_END |
| 89h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_OVL_WINDOW_START |
| 8Ah |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_OVL_WINDOW_END |
| 8Fh |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_ILLUMEN_START |
| 90h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_ILLUMEN_END |
| 91h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_CALC_START |
| 92h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_CALC_END |
| 93h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_DYNPDN_START |
| 94h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
TG_DYNPDN_END |
| 97h |
TG_SEQ_INT_MASK_END |
TG_SEQ_INT_MASK_START |
| 98h |
TG_CAPTURE_MASK_END |
TG_CAPTURE_MASK_START |
| 99h |
TG_OVL_WINDOW_MASK_END |
TG_OVL_WINDOW_MASK_START |
| 9Ch |
TG_ILLUMEN_MASK_END |
TG_ILLUMEN_MASK_START |
| 9Dh |
TG_CALC_MASK_END |
TG_CALC_MASK_START |
| 9Eh |
TG_DYNPDN_MASK_END |
TG_DYNPDN_MASK_START |
| 9Fh |
NUM_AVG_SUB_FRAMES |
NUM_SUB_FRAMES |
| A0h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
CAPTURE_CLK_CNT |
| A2h |
A3_COEFF_HDR0_TX1[15:8] |
A0_COEFF_HDR1_TX0 |
| A3h |
A3_COEFF_HDR0_TX1[7:0] |
A0_COEFF_HDR0_TX1 |
| A4h |
A3_COEFF_HDR1_TX1[15:8] |
A0_COEFF_HDR1_TX1 |
| A5h |
A3_COEFF_HDR1_TX1[7:0] |
A0_COEFF_HDR0_TX2 |
| A6h |
A3_COEFF_HDR0_TX2[15:8] |
A0_COEFF_HDR1_TX2 |
| A7h |
A3_COEFF_HDR0_TX2[7:0] |
A1_COEFF_HDR1_TX0 |
| A8h |
A3_COEFF_HDR1_TX2[15:8] |
A1_COEFF_HDR0_TX1 |
| A9h |
A3_COEFF_HDR1_TX2[7:0] |
A1_COEFF_HDR1_TX1 |
| AAh |
A4_COEFF_HDR1_TX0[15:8] |
A1_COEFF_HDR0_TX2 |
| ABh |
A4_COEFF_HDR1_TX0[7:0] |
A1_COEFF_HDR1_TX2 |
| ACh |
A4_COEFF_HDR0_TX1[15:8] |
A2_COEFF_HDR1_TX0 |
| ADh |
A4_COEFF_HDR0_TX1[7:0] |
A2_COEFF_HDR0_TX1 |
| AEh |
A4_COEFF_HDR1_TX1[15:8] |
A2_COEFF_HDR1_TX1 |
| AFh |
A4_COEFF_HDR1_TX1[7:0] |
A2_COEFF_HDR0_TX2 |
| B0h |
A4_COEFF_HDR0_TX2[15:8] |
A2_COEFF_HDR1_TX2 |
| B1h |
A4_COEFF_HDR0_TX2[7:0] |
A3_COEFF_HDR1_TX0 |
| B2h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
A4_COEFF_HDR1_TX2 |
| B4h |
AMB_PHASE_CORR_PWL_COEFF3 |
AMB_PHASE_CORR_PWL_COEFF2 |
AMB_PHASE_CORR_PWL_COEFF1 |
| B5h |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
SCALE_AMB_PHASE_CORR_COEFF |
| B8h |
0 |
0 |
0 |
GIVE_DEALIAS_DATA |
AMB_PHASE_CORR_PWL_X1 |
AMB_PHASE_CORR_PWL_X0 |
| B9h |
ILLUM_SCALE_H_TX2 |
ILLUM_SCALE_L_TX2 |
AMB_ADC_IN_TX2 |
AMB_ADC_IN_TX1 |
AMB_ADC_IN_TX0 |
EN_TX2_ON_TX0 |
EN_TX1_ON_TX0 |
AMB_PHASE_CORR_PWL_X2 |