ZHCSHP9C May   2017  – October 2018 IWR1443

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pin Multiplexing
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Supply Specifications
    6. 5.6 Power Consumption Summary
    7. 5.7 RF Specification
    8. 5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1  Power Supply Sequencing and Reset Timing
      2. 5.9.2  Synchronized Frame Triggering
      3. 5.9.3  Input Clocks and Oscillators
        1. 5.9.3.1 Clock Specifications
      4. 5.9.4  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.9.4.1 Peripheral Description
        2. 5.9.4.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-8  SPI Timing Conditions
          2. Table 5-9  SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-10 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.9.4.3 SPI Slave Mode I/O Timings
          1. Table 5-11 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.9.4.4 Typical Interface Protocol Diagram (Slave Mode)
      5. 5.9.5  LVDS Interface Configuration
        1. 5.9.5.1 LVDS Interface Timings
      6. 5.9.6  General-Purpose Input/Output
        1. Table 5-13 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 5.9.7  Controller Area Network Interface (DCAN)
        1. Table 5-14 Dynamic Characteristics for the DCANx TX and RX Pins
      8. 5.9.8  Serial Communication Interface (SCI)
        1. Table 5-15 SCI Timing Requirements
      9. 5.9.9  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-16 I2C Timing Requirements
      10. 5.9.10 Quad Serial Peripheral Interface (QSPI)
        1. Table 5-17 QSPI Timing Conditions
        2. Table 5-18 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-19 QSPI Switching Characteristics
      11. 5.9.11 JTAG Interface
        1. Table 5-20 JTAG Timing Conditions
        2. Table 5-21 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-22 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
      12. 5.9.12 Camera Serial Interface (CSI)
        1. Table 5-23 CSI Switching Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 External Interfaces
    4. 6.4 Subsystems
      1. 6.4.1 RF and Analog Subsystem
        1. 6.4.1.1 Clock Subsystem
        2. 6.4.1.2 Transmit Subsystem
        3. 6.4.1.3 Receive Subsystem
        4. 6.4.1.4 Radio Processor Subsystem
      2. 6.4.2 Master (Control) System
      3. 6.4.3 Host Interface
    5. 6.5 Accelerators and Coprocessors
    6. 6.6 Other Subsystems
      1. 6.6.1 A2D Data Format Over CSI2 Interface
      2. 6.6.2 ADC Channels (Service) for User Application
        1. Table 6-2 GP-ADC Parameter
    7. 6.7 Identification
    8. 6.8 Boot Modes
      1. 6.8.1 Flashing Mode
      2. 6.8.2 Functional Mode
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Reference Schematic
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
      3. 7.3.3 Stackup Details
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Community Resources
    5. 8.5 商标
    6. 8.6 静电放电警告
    7. 8.7 Export Control Notice
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

6.4.2 Master (Control) System

The Master (Control) System includes ARM’s Cortex-R4F processor clocked at 200 MHz, which is user programmable. User applications executing on this processor control the overall operation of the device, including Radar Control via well-defined API messages, radar signal processing (assisted by the radar hardware accelerator) and peripherals for external interface.

The Master (Control) System plays a big role in enabling autonomous operation of IWR1443 as a radar-on-a-chip sensor. The device includes a quad serial peripheral interface (QSPI) which can be used to download customer code directly from a serial flash. A (classic) CAN interface is included that can be used to communicate directly from the device to a CAN bus. An SPI/I2C interface is available for power management IC (PMIC) control when the IWR1443 is used as an autonomous sensor.

For more complex applications, the device can operate under the control of an external MCU, which can communicate with IWR1443 device over an SPI interface. In this case, it is possible to use the IWR14xx as a radar sensor, providing raw detected objects to the external MCU. External MCU could reduce the application code complexity residing in the device and makes more memory available for radar data cube inside the IWR1443. This configuration also eliminates the need for a separate serial flash to be connected to the IWR1443.

The IWR1443 provides for several digital communications outputs; CSI-2 Clk, 4 data formats – can be connected to a remote processor for additional processing. Note: CSI-2 data is from the digital front end or accelerator. When the MSS is used for preprocessing / or another MCU is used in industrial settings the Serial Tx/Rx or CAN bus can provide lower speed communication than CSI-2. The IWR1443 has additional serial Tx/Rx for HART protocol for industrial sensors, or Modbus serial protocol. The SPI port can also provide additional communications or IO control. Additional industrial IO can be Industrial Ethernet or Wifi.

Note that although four interfaces – one CAN, one I2C and two SPI interfaces – are present in the IWR1443 device for external communication and PMIC control, only two of these interfaces are usable at any point in time.

The total memory (RAM) available in the master subsystem is 576 KB. This is partitioned between the R4F program RAM, R4F data RAM and radar data memory. The maximum usable size for R4F is 448 KB and this is partitioned between the R4F’s tightly coupled interfaces TCMA (320 KB) and TCMB (128 KB). Although the complete 448 KB is unified memory and can be used for program or data, typical applications use TCMA as program and TCMB as data memory.

The remaining memory, starting at a minimum of 128 KB, is available to be used as radar data memory for storing the ‘radar data cube’. It is possible to increase the radar data memory size in 64 KB increments, at the cost of corresponding reduction in R4F program or data RAM size. The maximum size of radar data memory possible is 384 KB. A few example configurations supported are listed in Table 6-1.

Table 6-1 R4F RAM(1)

OPTION R4F PROGRAM RAM R4F DATA RAM RADAR DATA MEMORY
1 320KB 128KB 128KB
2 256KB 128KB 192KB
3 256KB 64KB 256KB
4 128KB 64KB 384KB
(1) For IWR1443 ES1.0 and ES2.0, available RAM is 448 KB instead of 576KB.

The Master Subsystem Memory Map is shown in the Technical Reference Manual.