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LMK05028 是一款高性能网络同步器时钟器件,提供抖动消除、时钟生成、高级时钟监控和优秀的无中断切换性能,可满足通信基础设施和工业应用的严格时序要求。该器件具有低抖动和高 PSNR 性能,可降低高速串行链路中的误码率 (BER)。
该器件具有两个 PLL 通道,最多可生成八个输出时钟(抖动低至 150-fs RMS)。每个 PLL 域可从任意四个基准输入中进行选择,以同步输出。
PIN | TYPE(1) | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | NO. | ||||
POWER | |||||
GND | PAD | G | Ground / Thermal
Pad.
The exposed pad must be connected to PCB ground for proper electrical and thermal performance. A 7×7 via pattern is recommended to connect the IC ground pad to the PCB ground layers. | ||
VDD_IN0 | 3 | P | Core Supply (3.3 V) for Reference Inputs 0 to 3. Place a nearby 0.1-µF bypass capacitor on each pin. | ||
VDD_IN1 | 16 | P | |||
VDD_IN2 | 9 | P | |||
VDD_IN3 | 4 | P | |||
VDD_XO | 42 | P | Core Supply (3.3 V) for XO and TCXO Inputs. Place a nearby 0.1-µF bypass capacitor on each pin. | ||
VDD_TCXO | 19 | P | |||
VDD_APLL1 | 49 | P | Core Supply (3.3 V) for PLL1, PLL2, and Digital Blocks. Place a nearby 0.1-µF bypass capacitor on each pin. | ||
VDD_APLL2 | 37 | P | |||
VDD_DIG | 8 | P | |||
VDDO_0 | 21 | P | Output Supply (1.8, 2.5, or 3.3 V) for Clock Outputs 0 to 7. Place a nearby 0.1-µF bypass capacitor on each pin. | ||
VDDO_1 | 25 | P | |||
VDDO_23 | 30 | P | |||
VDDO_45 | 50 | P | |||
VDDO_6 | 59 | P | |||
VDDO_7 | 63 | P | |||
CORE BLOCKS | |||||
LF1 | 47 | A | External Loop Filter Capacitor for APLL1 and APLL2. Place a nearby 0.1-µF capacitor on each pin. | ||
LF2 | 39 | A | |||
CAP_APLL1 | 48 | A | External Bypass Capacitors for APLL1, APLL2, and Digital Blocks. Place a nearby 10-µF bypass capacitor on each pin. | ||
CAP_APLL2 | 38 | A | |||
CAP_DIG | 7 | A | |||
INPUT BLOCKS | |||||
IN0_P | 1 | I | DPLL Reference Clock Inputs 0 to 3. Each input pair can accept a differential or single-ended clock signal for synchronizing the DPLLs. Each pair has a programmable input type with internal termination to support AC- or DC-coupled clocks. A single-ended LVCMOS clock can be applied to the P input with the N input pulled down to ground. An unused input pair can be left floating. LVCMOS input mode is recommended for input frequencies less than 5 MHz. | ||
IN0_N | 2 | I | |||
IN1_P | 14 | I | |||
IN1_N | 15 | I | |||
IN2_P | 10 | I | |||
IN2_N | 11 | I | |||
IN3_P | 5 | I | |||
IN3_N | 6 | I | |||
XO_P | 43 | I | XO Input. This input pair can accept a differential or single-ended clock signal from a low-jitter local oscillator to lock the APLLs. This input has a programmable input type with internal termination to support AC- or DC-coupled clocks. A single-ended LVCMOS clock (up to 2.5 V) can be applied to the P input with the N input pulled down to ground. | ||
XO_N | 44 | I | |||
TCXO_IN | 18 | I | TCXO Input. This input can accept an AC-coupled sinewave, clipped-sinewave, or single-ended clock signal from a stable oscillator (TCXO/OCXO) to lock the TCXO-DPLL if used by a DPLL configuration. The input swing must be less than 1.3 Vpp before AC-coupling to the input pin, which has weak internal biasing of 0.6 V and no internal termination. Leave pin floating if unused. | ||
OUTPUT BLOCKS | |||||
OUT0_P | 22 | O | Clock Outputs 0 to 3 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or 1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs must be terminated if active or left floating if disabled through registers. The OUT[0:3] bank requires at least one clock from the PLL2 domain if enabled. This bank is preferred for PLL2 clocks to minimize output crosstalk. | ||
OUT0_N | 23 | O | |||
OUT1_P | 27 | O | |||
OUT1_N | 26 | O | |||
OUT2_P | 31 | O | |||
OUT2_N | 32 | O | |||
OUT3_P | 34 | O | |||
OUT3_N | 33 | O | |||
OUT4_P | 51 | O | Clock Outputs 4 to 7 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or 1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs must be terminated if active or left floating if disabled through registers. The OUT[4:7] bank requires at least one clock from the PLL1 domain. This bank is preferred for PLL1 clocks to minimize output crosstalk. | ||
OUT4_N | 52 | O | |||
OUT5_P | 54 | O | |||
OUT5_N | 53 | O | |||
OUT6_P | 57 | O | |||
OUT6_N | 58 | O | |||
OUT7_P | 62 | O | |||
OUT7_N | 61 | O | |||
LOGIC CONTROL / STATUS (2)(3) | |||||
HW_SW_CTRL | 64 | I | Device Start-Up Mode Select (3-level, 1.8-V compatible). This input selects the device start-up mode that determines the memory page used to initialize the registers, serial interface, and logic pin functions. The input level is sampled only at device power-on reset (POR). See Table 4-2 for start-up mode descriptions and logic pin functions. | ||
PDN | 46 | I | Device Power-Down (active low). When PDN is pulled low, the device is in hard reset and all blocks including the serial interface are powered down. When PDN is pulled high, the device is started according to device mode selected by HW_SW_CTRL and begins normal operation with all internal circuits reset to their initial state. | ||
SDA/SDI | 35 | I/O | I2C Serial Data I/O (SDA) or SPI Serial Data Input (SDI). See Table 4-2. The default 7-bit I2C address is 11000xxb, where the MSB bits (11000b) are initialized from on-chip EEPROM and the LSB bits (xxb) are determined by the logic input pins. When HW_SW_CTRL is 0, the LSBs are determined by the GPIO[2:1] input levels during POR. When HW_SW_CTRL is 1, the LSBs are fixed to 00b. | ||
SCL/SCK | 36 | I | I2C Serial Clock Input (SCL) or SPI Serial Clock Input (SCK). See Table 4-2. | ||
GPIO0/SYNCN | 45 | I | Multifunction Inputs or Outputs. See Table 4-2. | ||
GPIO1/SCS | 24 | I | |||
GPIO2/SDO | 60 | I/O | |||
GPIO3/FINC1 | 40 | I | |||
GPIO4/FDEC1 | 41 | I | |||
GPIO5/FINC2 | 12 | I/O | |||
GPIO6/FDEC2 | 13 | I/O | |||
STATUS1 | 56 | I/O | Status Outputs [1:0]. Each output has programmable status signal selection, driver type (3.3-V LVCMOS or open-drain), and status polarity. Open-drain requires an external pullup resistor. Leave pin floating if unused. | ||
STATUS0 | 55 | I/O | |||
INSEL0_1 | 17 | I | Manual Reference Input Selection for DPLL1. INSEL0_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused. | ||
INSEL0_0 | 20 | I | |||
INSEL1_1 | 29 | I | Manual Reference Input Selection for DPLL2. INSEL1_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused. | ||
INSEL1_0 | 28 | I |
The HW_SW_CTRL input pin selects the device start-up mode that determines the memory page used to initialize the registers, serial interface, and logic pin functions at power-on reset. The initial register settings determine the device's frequency configuration stored in the internal EEPROM (NVM) or ROM. After start-up, the device registers can be accessed through the selected serial interface for device status monitoring or programming, and the logic pins will function as defined by the mode configuration.
HW_SW_CTRL INPUT LEVEL(1) | START-UP MODE | MODE DESCRIPTION |
---|---|---|
0 | EEPROM + I2C (Soft pin mode) | Registers are initialized from EEPROM, and I2C interface is enabled. Logic pins:
|
Float (VIM) | EEPROM + SPI (Soft pin mode) | Registers are initialized from EEPROM, and SPI interface is enabled. Logic pins:
|
1 | ROM + I2C (Hard pin mode) | Registers are initialized from the ROM page selected by GPIO pins, and I2C interface is enabled. Logic pins:
After POR, GPIO[6:3] can function the same as for HW_SW_CTRL = 0 if enabled by registers. |
To provide proper start-up into EEPROM + SPI Mode, the HW_SW_CTRL, STATUS0, and STATUS1 pins must all be floating or biased to VIM (0.8-V typical) before the PDN pin is pulled high. These three pins momentarily operate as 3-level inputs and get sampled at the low-to-high transition of PDN to determine the device start-up mode during POR. If any of these pins are connected to a host device (MCU or FPGA), TI recommends using external biasing resistors on each pin (10-kΩ pullup to 3.3 V with 3.3-kΩ pulldown to GND) to set the inputs to VIM during POR. After power-up, the STATUS pins can operate as LVCMOS outputs to overdrive the external resistor bias for normal status operation.
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD(2) | Core supply voltages | -0.3 | 3.6 | V |
VDDO(3) | Output supply voltages | -0.3 | 3.6 | V |
VIN | Input voltage range for clock and logic inputs | -0.3 | VDD+0.3 | V |
VOUT_LOGIC | Output voltage range for logic outputs | -0.3 | VDD+0.3 | V |
VOUT | Output voltage range for clock outputs | -0.3 | VDDO+0.3 | V |
Tj | Junction temperature | 150 | °C | |
Tstg | Storage temperature range | -65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±750 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDD(1) | Core supply voltages | 3.135 | 3.3 | 3.465 | V |
VDDO_x(2) | Output supply voltage for AC-LVDS/CML/LVPECL or HCSL driver | 1.71 | 1.8, 2.5, 3.3 | 3.465 | V |
VDDO_x(2) | Output supply voltage for 1.8-V LVCMOS driver(3) | 1.71 | 1.8 | 1.89 | V |
VDDO_x(2) | Output supply voltage for 2.5-V LVCMOS driver(3) | 2.375 | 2.5 | 2.625 | V |
VIN | Input voltage range for clock and logic inputs | 0 | 3.465 | V | |
TJ | Junction temperature | 135 | °C | ||
tVDD | Power supply ramp time(4) | 0.01 | 100 | ms | |
nEEcyc | EEPROM program cycles(6) | 100 | cycles | ||
SROUT | Output slew rate mode(5) | Fast | - |