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  • DAC874xH HART® 和 FOUNDATION Fieldbus™ 以及 PROFIBUS PA 调制解调器

    • ZHCSH77D June   2017  – May 2019 DAC8740H , DAC8741H

      PRODUCTION DATA.  

  • CONTENTS
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  • DAC874xH HART® 和 FOUNDATION Fieldbus™ 以及 PROFIBUS PA 调制解调器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: DAC8740H
    2.     Pin Functions: DAC8741H
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  HART Modulator
      2. 8.3.2  HART Demodulator
      3. 8.3.3  FOUNDATION Fieldbus or PROFIBUS PA Manchester Encoder
      4. 8.3.4  FOUNDATION Fieldbus or PROFIBUS PA Manchester Decoder
      5. 8.3.5  Internal Reference
      6. 8.3.6  Clock Configuration
      7. 8.3.7  Reset and Power-Down
      8. 8.3.8  Full-Duplex Mode
      9. 8.3.9  I/O Selection
      10. 8.3.10 Jabber Inhibitor
    4. 8.4 Device Functional Modes
      1. 8.4.1 UART Interfaced HART
      2. 8.4.2 UART Interfaced FOUNDATION Fieldbus or PROFIBUS PA
      3. 8.4.3 SPI Interfaced HART
      4. 8.4.4 SPI Interfaced FOUNDATION Fieldbus or PROFIBUS PA
      5. 8.4.5 Digital Interface
        1. 8.4.5.1 UART
          1. 8.4.5.1.1 UART Carrier Detect
        2. 8.4.5.2 SPI
          1. 8.4.5.2.1 SPI Cyclic Redundancy Check
          2. 8.4.5.2.2 SPI Interrupt Request
    5. 8.5 Register Maps
      1. 8.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
        1. Table 9. CONTROL Register Field Descriptions
      2. 8.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
        1. Table 10. RESET Register Field Descriptions
      3. 8.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
        1. Table 11. MODEM_STATUS Register Field Descriptions
      4. 8.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
        1. Table 12. MODEM_IRQ_MASK Register Field Descriptions
      5. 8.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
        1. Table 13. MODEM_CONTROL Register Field Descriptions
      6. 8.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
        1. Table 14. FIFO_D2M Register Field Descriptions
      7. 8.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
        1. Table 15. FIFO_M2D Register Field Descriptions
      8. 8.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
        1. Table 16. FIFO_LEVEL_SET Register Field Descriptions
      9. 8.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
        1. Table 17. PAFF_JABBER Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design Recommendations
      2. 9.1.2 Selecting the Crystal or Resonator
      3. 9.1.3 Included Functions and Filter Selection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DAC8740H HART Modem
        2. 9.2.2.2 2-Wire Current Loop
        3. 9.2.2.3 Regulator
        4. 9.2.2.4 DAC
        5. 9.2.2.5 Amplifiers
        6. 9.2.2.6 Diodes
        7. 9.2.2.7 Passives
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 相关链接
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

DAC874xH HART® 和 FOUNDATION Fieldbus™ 以及 PROFIBUS PA 调制解调器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 兼容 HART 的物理层调制解调器
    • 1200Hz、2200Hz HART FSK 正弦波
    • TX 信号振幅的寄存器编程控制（仅适用于 DAC8741H）
    • 集成式 RX 解调器和带通滤波器，具有极少的外部组件
  • 兼容 FOUNDATION 现场总线的 H1 控制器和介质连接单元 (MAU)
    • 基于曼彻斯特编码总线供电 (MBP) 的 31.25kbit/s 通信
    • 集成曼彻斯特编码器和解码器
    • 与 PROFIBUS PA 兼容
  • 低静态电流：在典型工业工作温度范围（-40°C 至 +85°C）下最大值为 180µA
  • 集成 1.5V 电压基准
  • 灵活的时钟选项
    • 内部振荡器
    • 外部晶体振荡器
    • 外部 CMOS 时钟
  • 数字接口
    • DAC8740H：UART
    • DAC8741H：SPI
  • 可靠性：CRC 位错校验、看门狗计时器（仅适用于 DAC8741H）
  • 宽工作温度范围：–55°C 至 +125°C
  • 4mm × 4mm QFN 封装
    • DAC8740H DAC8741H HART_CP_Logo.gif

2 应用

  • 工业过程控制和自动化
  • PLC 或 DCS I/O 模块
  • 现场和传感器变送器

3 说明

DAC8740H 和 DAC8741H (DAC874xH) 是与 HART®、 FOUNDATION 现场总线™和 PROFIBUS PA 兼容的低功耗调制解调器，设计用于工业过程控制和工业自动化 应用。

在 HART 模式下，DAC874xH 集成所有必需电路，以作为一个半双工 HART 物理层调制解调器，在从配置或主配置中使用最少的外部过滤组件运行。在 FOUNDATION 现场总线模式下，DAC874xH 集成所有必需电路，以作为兼容半双工 FOUNDATION 现场总线的 H1 控制器和 MAU 运行。

在 HART、FOUNDATION 现场总线或 PROFIBUS PA 模式下，可通过 UART 接口或 SPI 接口接入的集成式 FIFO 传输来自微控制器的数据流。SPI 接口包括一个支持菊链的 SDO 引脚、各种中断以及其他扩展 特性。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
DAC8740H 超薄四方扁平无引线 (VQFN) (24) 4mm x 4mm
DAC8741H 超薄四方扁平无引线 (VQFN) (24) 4mm x 4mm
  1. 要了解所有可用封装，请参见数据表末尾的封装选项附录。

Device Images

简化原理图

DAC8740H DAC8741H SBAS856_BlockDiagram.gif

4 修订历史记录

Changes from C Revision (December 2018) to D Revision

  • Added recommended operating temperature range, TA, to the Recommended Operating Conditions tableGo
  • Changed maximum temperature test conditions for all specifications in the Electrical Characteristics table from +125℃ to +105℃Go

Changes from B Revision (June 2018) to C Revision

  • Deleted 从数据表中删除了 DAC8742HGo

Changes from A Revision (December 2017) to B Revision

  • DAC8741H 和 DAC8742H 已发布至生产Go

Changes from * Revision (June 2017) to A Revision

  • 首次公开发布的完整数据表Go
  • DAC8740H 已发布至生产Go

5 Device Comparison Table

PART NUMBER DIGITAL INTERFACE
DAC8740H UART
DAC8741H SPI

6 Pin Configuration and Functions

RGE Package: DAC8740H
24-Pin VQFN
Top View

Pin Functions: DAC8740H

PIN TYPE DESCRIPTION
NO. NAME
1 XEN Digital input Crystal oscillator enable. Logic low on this pin enables the crystal oscillator circuit; in this mode, an external crystal is required. Logic high on this pin disables the internal crystal oscillator circuit; in this mode an external CMOS clock or the internal oscillator are required. No digital input pin should be left floating.
2 CLKO Digital output Clock output. If using the internal oscillator or an external crystal, this pin can be configured as a clock output.
3 CLK_CFG0 Digital input Clock configuration. This pin is used to configure the input/output clocking scheme. No digital input pin should be left floating.
4 CLK_CFG1 Digital input Clock configuration. This pin is used to configure the input/output clocking scheme. No digital input pin should be left floating.
5 RST Digital input Reset. Logic low on this pin places the DAC874xH into power-down mode and resets the device. Logic high returns the device to normal operation. No digital input pin should be left floating.
6 CD Digital output HART mode.
Carrier detect. A logic high on this pin indicates a valid carrier is present.
FF or PA mode.
While not transmitting, a logic high on this pin indicates a valid carrier is present. While transmitting, a logic high on this pin indicates that the jabber inhibitor has triggered.
7 UART_IN Digital input UART data input. No digital input pin should be left floating.
8 UART_RTS Digital input,
Digital output		 HART mode.
Request to send. A logic high on this pin enables the demodulator and disables the modulator. A logic low on this pin enables the modulator and disables the demodulator. No digital input pin should be left floating.
FF or PA mode.
This pin reports transmit FIFO threshold information as programmed by the packet initiation code.
9 DUPLEX Digital input Digital input. Logic high enables full-duplex, or internal loop-back, test mode. No digital input pin should be left floating.
10 UART_OUT Digital output UART data output
11 IOVDD Supply Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interface.
12 GND Supply Digital ground. Ground reference voltage for all digital circuitry of the device.
13 REG_CAP Analog output Capacitor for internal regulator.
14 MOD_OUT Analog output Modem output. FSK output sinusoid in HART mode or Manchester coded data stream in FOUNDATION Fieldbus and PROFIBUS PA modes. for stability, this pin requires parallel capacitance of 5 nF to 22 nF in HART mode, or 0 pF to 100 pF in FOUNDATION Fieldbus and PROFIBUS PA mode.
15 REF Analog input or
output		 When the internal reference is enabled, this pin outputs the internal reference voltage. When the internal reference is disabled, this pin is the external 2.5-V reference input.
16 MOD_IN Analog input HART FSK input or FOUNDATION Fieldbus and PROFIBUS PA Manchester coded data stream input. If an external filter is used, do not connect this pin.
17 MOD_INF Analog input If using the internal band-pass filter, connect 680 pF to this pin in HART mode, or 120 pF in FOUNDATION Fieldbus and PROFIBUS PA modes. If using an external filter, connect the output of that filter to this pin.
18 AVDD Supply Power supply
19 GND Supply Analog ground. Ground reference voltage for power supply input.
20 X2 Analog input Crystal stimulus
21 X1 Analog input Crystal ro clock input
22 GND Supply Digital ground. Ground reference voltage for all digital circuitry of the device.
23 REF_EN Digital input Reference enable. Logic high enables the internal 1.5-V reference. No digital input pin should be left floating.
24 BPF_EN Digital input Filter enable. A logic high enables the internal band-pass filter. No digital input pin should be left floating.
Thermal pad Thermal pad Supply Thermal pad. Connected to GND if connected to an electrical potential.
RGE Package: DAC8741H
24-Pin VQFN
Top View

Pin Functions: DAC8741H

PIN TYPE DESCRIPTION
NO. NAME
1 XEN Digital input Crystal oscillator enable. Logic low on this pin enables the crystal oscillator circuit; in this mode, an external crystal is required. Logic high on this pin disables the internal crystal oscillator circuit; in this mode, an external CMOS clock or the internal oscillator are required. No digital input pin should be left floating.
2 CLKO Digital output Clock output. If using the internal oscillator or an external crystal, this pin can be configured as a clock output.
3 CLK_CFG0 Digital input Clock configuration. This pin is used to configure the input/output clocking scheme. No digital input pin should be left floating.
4 CLK_CFG1 Digital input Clock Configuration. This pin is used to configure the input/output clocking scheme. No digital input pin should be left floating.
5 RST Digital input Reset. Logic low on this pin places the DAC874xH into power-down mode and resets the device. Logic high returns the device to normal operation. No digital input pin should be left floating.
6 IRQ Digital output Digital Interrupt. The interrupt can be configured as edge sensitive or level sensitive with positive or negative polarity, as set by the CONTROL register. Events that trigger an interrupt are controlled by the Modem IRQ Mask register.
7 CS Digital input SPI chip-select. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in a high-impedance state and data on SDI are ignored. No digital input pin should be left floating.
8 SCLK Digital input SPI clock. Data can be transferred at rates up to 12.5 MHz. Schmitt-Trigger logic input. No digital input pin should be left floating.
9 SDI Digital input SPI data input. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. Schmitt-Trigger logic input. No digital input pin should be left floating.
10 SDO Digital output SPI data output. Data are valid on the falling edge of SCLK.
11 IOVDD Supply Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interface.
12 GND Supply Digital ground. Ground reference voltage for all digital circuitry of the device.
13 REG_CAP Analog output Capacitor for internal regulator
14 MOD_OUT Analog output Modem output. FSK output sinusoid in HART mode or Manchester coded data stream in FOUNDATION Fieldbus and PROFIBUS PA modes. For stability, this pin requires parallel capacitance of 5 nF to 22 nF in HART mode, or 0 pF to 100 pF in FOUNDATION Fieldbus and PROFIBUS PA mode.
15 REF Analog Input or
output		 When the internal reference is enabled, this pin outputs the internal reference voltage. When the internal reference is disabled, this pin is the external 2.5-V reference input.
16 MOD_IN Analog input HART FSK input or FOUNDATION Fieldbus and PROFIBUS PA Manchester coded data stream input. If an external filter is used, do not connect this pin.
17 MOD_INF Analog input If using the internal band-pass filter, connect 680 pF to this pin, or 120 pF in FOUNDATION Fieldbus and PROFIBUS PA modes. If using an external filter, connect the output of that filter to this pin.
18 AVDD Supply Power supply
19 GND Supply Analog ground. Ground reference voltage for power supply input.
20 X2 Analog input Crystal stimulus
21 X1 Analog input Crystal or clock input
22 GND Supply Digital ground. Ground reference voltage for all digital circuitry of the device.
23 REF_EN Digital input Reference enable. Logic high enables the internal 1.5-V reference. No digital input pin should be left floating.
24 BPF_EN Digital input Filter enable. A logic high enables the internal band-pass filter. No digital input pin should be left floating.
Thermal pad Thermal pad Supply Thermal pad. Connected to GND if connected to an electrical potential.

7 Specifications

 
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