DAC8740H 和 DAC8741H (DAC874xH) 是与 HART®、 FOUNDATION 现场总线™和 PROFIBUS PA 兼容的低功耗调制解调器,设计用于工业过程控制和工业自动化 应用。
在 HART 模式下,DAC874xH 集成所有必需电路,以作为一个半双工 HART 物理层调制解调器,在从配置或主配置中使用最少的外部过滤组件运行。在 FOUNDATION 现场总线模式下,DAC874xH 集成所有必需电路,以作为兼容半双工 FOUNDATION 现场总线的 H1 控制器和 MAU 运行。
在 HART、FOUNDATION 现场总线或 PROFIBUS PA 模式下,可通过 UART 接口或 SPI 接口接入的集成式 FIFO 传输来自微控制器的数据流。SPI 接口包括一个支持菊链的 SDO 引脚、各种中断以及其他扩展 特性。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
DAC8740H | 超薄四方扁平无引线 (VQFN) (24) | 4mm x 4mm |
DAC8741H | 超薄四方扁平无引线 (VQFN) (24) | 4mm x 4mm |
Changes from C Revision (December 2018) to D Revision
Changes from B Revision (June 2018) to C Revision
Changes from A Revision (December 2017) to B Revision
Changes from * Revision (June 2017) to A Revision
PART NUMBER | DIGITAL INTERFACE |
---|---|
DAC8740H | UART |
DAC8741H | SPI |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | XEN | Digital input | Crystal oscillator enable. Logic low on this pin enables the crystal oscillator circuit; in this mode, an external crystal is required. Logic high on this pin disables the internal crystal oscillator circuit; in this mode an external CMOS clock or the internal oscillator are required. No digital input pin should be left floating. |
2 | CLKO | Digital output | Clock output. If using the internal oscillator or an external crystal, this pin can be configured as a clock output. |
3 | CLK_CFG0 | Digital input | Clock configuration. This pin is used to configure the input/output clocking scheme. No digital input pin should be left floating. |
4 | CLK_CFG1 | Digital input | Clock configuration. This pin is used to configure the input/output clocking scheme. No digital input pin should be left floating. |
5 | RST | Digital input | Reset. Logic low on this pin places the DAC874xH into power-down mode and resets the device. Logic high returns the device to normal operation. No digital input pin should be left floating. |
6 | CD | Digital output | HART mode.
Carrier detect. A logic high on this pin indicates a valid carrier is present. |
FF or PA mode.
While not transmitting, a logic high on this pin indicates a valid carrier is present. While transmitting, a logic high on this pin indicates that the jabber inhibitor has triggered. |
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7 | UART_IN | Digital input | UART data input. No digital input pin should be left floating. |
8 | UART_RTS | Digital input,
Digital output |
HART mode.
Request to send. A logic high on this pin enables the demodulator and disables the modulator. A logic low on this pin enables the modulator and disables the demodulator. No digital input pin should be left floating. |
FF or PA mode.
This pin reports transmit FIFO threshold information as programmed by the packet initiation code. |
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9 | DUPLEX | Digital input | Digital input. Logic high enables full-duplex, or internal loop-back, test mode. No digital input pin should be left floating. |
10 | UART_OUT | Digital output | UART data output |
11 | IOVDD | Supply | Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interface. |
12 | GND | Supply | Digital ground. Ground reference voltage for all digital circuitry of the device. |
13 | REG_CAP | Analog output | Capacitor for internal regulator. |
14 | MOD_OUT | Analog output | Modem output. FSK output sinusoid in HART mode or Manchester coded data stream in FOUNDATION Fieldbus and PROFIBUS PA modes. for stability, this pin requires parallel capacitance of 5 nF to 22 nF in HART mode, or 0 pF to 100 pF in FOUNDATION Fieldbus and PROFIBUS PA mode. |
15 | REF | Analog input or
output |
When the internal reference is enabled, this pin outputs the internal reference voltage. When the internal reference is disabled, this pin is the external 2.5-V reference input. |
16 | MOD_IN | Analog input | HART FSK input or FOUNDATION Fieldbus and PROFIBUS PA Manchester coded data stream input. If an external filter is used, do not connect this pin. |
17 | MOD_INF | Analog input | If using the internal band-pass filter, connect 680 pF to this pin in HART mode, or 120 pF in FOUNDATION Fieldbus and PROFIBUS PA modes. If using an external filter, connect the output of that filter to this pin. |
18 | AVDD | Supply | Power supply |
19 | GND | Supply | Analog ground. Ground reference voltage for power supply input. |
20 | X2 | Analog input | Crystal stimulus |
21 | X1 | Analog input | Crystal ro clock input |
22 | GND | Supply | Digital ground. Ground reference voltage for all digital circuitry of the device. |
23 | REF_EN | Digital input | Reference enable. Logic high enables the internal 1.5-V reference. No digital input pin should be left floating. |
24 | BPF_EN | Digital input | Filter enable. A logic high enables the internal band-pass filter. No digital input pin should be left floating. |
Thermal pad | Thermal pad | Supply | Thermal pad. Connected to GND if connected to an electrical potential. |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | XEN | Digital input | Crystal oscillator enable. Logic low on this pin enables the crystal oscillator circuit; in this mode, an external crystal is required. Logic high on this pin disables the internal crystal oscillator circuit; in this mode, an external CMOS clock or the internal oscillator are required. No digital input pin should be left floating. |
2 | CLKO | Digital output | Clock output. If using the internal oscillator or an external crystal, this pin can be configured as a clock output. |
3 | CLK_CFG0 | Digital input | Clock configuration. This pin is used to configure the input/output clocking scheme. No digital input pin should be left floating. |
4 | CLK_CFG1 | Digital input | Clock Configuration. This pin is used to configure the input/output clocking scheme. No digital input pin should be left floating. |
5 | RST | Digital input | Reset. Logic low on this pin places the DAC874xH into power-down mode and resets the device. Logic high returns the device to normal operation. No digital input pin should be left floating. |
6 | IRQ | Digital output | Digital Interrupt. The interrupt can be configured as edge sensitive or level sensitive with positive or negative polarity, as set by the CONTROL register. Events that trigger an interrupt are controlled by the Modem IRQ Mask register. |
7 | CS | Digital input | SPI chip-select. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in a high-impedance state and data on SDI are ignored. No digital input pin should be left floating. |
8 | SCLK | Digital input | SPI clock. Data can be transferred at rates up to 12.5 MHz. Schmitt-Trigger logic input. No digital input pin should be left floating. |
9 | SDI | Digital input | SPI data input. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. Schmitt-Trigger logic input. No digital input pin should be left floating. |
10 | SDO | Digital output | SPI data output. Data are valid on the falling edge of SCLK. |
11 | IOVDD | Supply | Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interface. |
12 | GND | Supply | Digital ground. Ground reference voltage for all digital circuitry of the device. |
13 | REG_CAP | Analog output | Capacitor for internal regulator |
14 | MOD_OUT | Analog output | Modem output. FSK output sinusoid in HART mode or Manchester coded data stream in FOUNDATION Fieldbus and PROFIBUS PA modes. For stability, this pin requires parallel capacitance of 5 nF to 22 nF in HART mode, or 0 pF to 100 pF in FOUNDATION Fieldbus and PROFIBUS PA mode. |
15 | REF | Analog Input or
output |
When the internal reference is enabled, this pin outputs the internal reference voltage. When the internal reference is disabled, this pin is the external 2.5-V reference input. |
16 | MOD_IN | Analog input | HART FSK input or FOUNDATION Fieldbus and PROFIBUS PA Manchester coded data stream input. If an external filter is used, do not connect this pin. |
17 | MOD_INF | Analog input | If using the internal band-pass filter, connect 680 pF to this pin, or 120 pF in FOUNDATION Fieldbus and PROFIBUS PA modes. If using an external filter, connect the output of that filter to this pin. |
18 | AVDD | Supply | Power supply |
19 | GND | Supply | Analog ground. Ground reference voltage for power supply input. |
20 | X2 | Analog input | Crystal stimulus |
21 | X1 | Analog input | Crystal or clock input |
22 | GND | Supply | Digital ground. Ground reference voltage for all digital circuitry of the device. |
23 | REF_EN | Digital input | Reference enable. Logic high enables the internal 1.5-V reference. No digital input pin should be left floating. |
24 | BPF_EN | Digital input | Filter enable. A logic high enables the internal band-pass filter. No digital input pin should be left floating. |
Thermal pad | Thermal pad | Supply | Thermal pad. Connected to GND if connected to an electrical potential. |