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  • IWR1642 单芯片 76 至 81GHz 毫米波传感器

    • ZHCSH27B May   2017  – April 2018 IWR1642

      PRODUCTION DATA.  

  • CONTENTS
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  • IWR1642 单芯片 76 至 81GHz 毫米波传感器
  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
      1. Table 4-3 PAD IO Register Bit Descriptions
    3. 4.3 Signal Descriptions
      1. Table 4-4 Signal Descriptions - Digital
      2. Table 4-5 Signal Descriptions - Analog
    4. 4.4 Pin Multiplexing
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Supply Specifications
    6. 5.6  Power Consumption Summary
    7. 5.7  RF Specification
    8. 5.8  CPU Specifications
    9. 5.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 5.10 Timing and Switching Characteristics
      1. 5.10.1  Power Supply Sequencing and Reset Timing
      2. 5.10.2  Input Clocks and Oscillators
        1. 5.10.2.1 Clock Specifications
      3. 5.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.10.3.1 Peripheral Description
        2. 5.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-7   SPI Timing Conditions
          2. Table 5-8   SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-9   SPI Master Mode Input Timing Requirements (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          4. Table 5-10 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          5. Table 5-11 SPI Master Mode Input Requirements (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.10.3.3 SPI Slave Mode I/O Timings
          1. Table 5-12 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          2. Table 5-13 SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 5.10.4  LVDS Interface Configuration
        1. 5.10.4.1 LVDS Interface Timings
      5. 5.10.5  General-Purpose Input/Output
        1. Table 5-15 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 5.10.6  Controller Area Network Interface (DCAN)
        1. Table 5-16 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 5.10.7  Serial Communication Interface (SCI)
        1. Table 5-17 SCI Timing Requirements
      8. 5.10.8  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-18 I2C Timing Requirements
      9. 5.10.9  Quad Serial Peripheral Interface (QSPI)
        1. Table 5-19 QSPI Timing Conditions
        2. Table 5-20 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-21 QSPI Switching Characteristics
      10. 5.10.10 ETM Trace Interface
        1. Table 5-22 ETMTRACE Timing Conditions
        2. Table 5-23 ETM TRACE Switching Characteristics
      11. 5.10.11 Data Modification Module (DMM)
        1. Table 5-24 DMM Timing Requirements
      12. 5.10.12 JTAG Interface
        1. Table 5-25 JTAG Timing Conditions
        2. Table 5-26 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-27 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Processor Subsystem
      3. 6.3.3 Host Interface
      4. 6.3.4 Master Subsystem Cortex-R4F Memory Map
      5. 6.3.5 DSP Subsystem Memory Map
    4. 6.4 Other Subsystems
      1. 6.4.1 ADC Channels (Service) for User Application
        1. Table 6-3 GP-ADC Parameter
  7. 7 Monitoring and Diagnostics
    1. 7.1 Monitoring and Diagnostic Mechanisms
      1. 7.1.1 Error Signaling Module
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Reference Schematic
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
      3. 8.3.3 Stackup Details
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Community Resources
    5. 9.5 商标
    6. 9.6 静电放电警告
    7. 9.7 出口管制提示
    8. 9.8 术语表
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information
  11. 重要声明
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DATA SHEET

IWR1642 单芯片 76 至 81GHz 毫米波传感器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 器件概述

1.1 特性

  • FMCW 收发器
    • 集成式 PLL、发送器、接收器、基带和 A2D
    • 76 至 81GHz 覆盖范围，具有 4GHz 的连续带宽
    • 四个接收通道
    • 两个发送通道
    • 基于分数 N PLL 的超精确线性调频脉冲（计时）引擎
    • TX 功率：12.5dBm
    • RX 噪声系数：
      • 14dB（76 至 77GHz）
      • 15dB（77 至 81GHz）
    • 1MHz 时的相位噪声：
      • –95dBc/Hz（76 至 77GHz）
      • –93dBc/Hz（77 至 81GHz）
  • 内置的校准和自检（监控）
    • 配备基于 ARM®Cortex®基于 ARM® Cortex®-R4F 的无线电控制系统
    • 内置的固件 (ROM)
    • 针对频率和温度进行自校准的系统
  • 用于 FMCW 信号处理的 C674x DSP
  • 片上存储器：1.5MB
  • 用于物体跟踪、分类和接口控制的 Cortex-R4F 微控制器
    • 支持自主模式（从 QSPI 闪存加载用户应用）
  • 具有 ECC 的内部存储器
  • 集成外设
    • 多达 6 个 ADC 通道
    • 多达 2 个 SPI 通道
    • 多达 2 个 UART
    • CAN 接口
    • I2C
    • GPIO
    • 用于原始 ADC 数据和调试仪表的 2 通道 LVDS 接口
  • IWR1642 高级 特性
    • 嵌入式自监控，无需使用主机处理器
    • 复基带架构
    • 嵌入式干扰检测功能
  • 电源管理
    • 内置的 LDO 网络，可增强 PSRR
    • I/O 支持双电压 3.3V/1.8V
  • 时钟源
    • 支持频率为 40MHz 的外部振荡器
    • 支持外部驱动、频率为 40MHz 的时钟（方波/正弦波）
    • 支持 40MHz 晶体与负载电容器相连接
  • 轻松的硬件设计
    • 0.65mm 间距、161 引脚 10.4mm × 10.4mm 覆晶 BGA 封装，可实现轻松组装和低成本 PCB 设计
    • 小尺寸解决方案
  • 运行条件
    • 结温范围:–40°C 至 105°C

1.2 应用

  • 用于测量距离、速度和角度的工业传感器
  • 液箱液位探测雷达
  • 位移感应
  • 现场发送器
  • 交通监控
  • 接近感应
  • 安全和监控
  • 工厂自动化安全防护装置
  • 人数统计
  • 运动检测
IWR1642 app_diagram_swrs212.gifFigure 1-1 适用于工业应用的自主 传感器

1.3 说明

IWR1642 器件是一款能够在 76 至 81GHz 频带中运行且基于 FMCW 雷达技术的集成式单芯片毫米波传感器，具有高达 4GHz 的连续线性调频脉冲。该器件采用 TI 的低功耗 45nm RFCMOS 工艺进行构建，并且此解决方案在极小的封装中实现了前所未有的集成度。IWR1642 是适用于工业 应用 （如楼宇自动化、工厂自动化、无人机、物料处理、交通监控和监视）中的低功耗、自监控、超精确雷达系统的理想解决方案。

IWR1642 器件是一种自包含单芯片解决方案，能够简化 76 至 81GHz 频带中的毫米波传感器实施。IWR1642 包含一个具有内置 PLL 和模数转换器的单片实施 2TX、4RX 系统。IWR1642 还集成了 DSP 子系统，该子系统包含 TI 用于雷达信号处理的高性能 C674x DSP。该器件包含一个基于 ARM R4F 的处理器子系统，该子系统负责前端配置、控制和校准。简单编程模型更改可支持各种传感器实施，并且能够进行动态重新配置，从而实现多模式传感器。此外，该器件作为完整的平台解决方案进行提供，该解决方案包括硬件参考设计、软件驱动程序、样例配置、API 指南、培训以及用户文档。

器件信息(1)

器件型号 封装 封装尺寸
IWR1642AQAGABL（托盘） FCBGA (161) 10.4mm × 10.4mm
IWR1642AQAGABLR（卷带封装）
(1) 更多信息请参见 Section 10，机械封装和可订购产品信息。

1.4 功能框图

IWR1642 fbd_swrs212.gif

2 修订历史记录

Changes from August 31, 2017 to April 30, 2018 (from A Revision () to B Revision)

  • 将 TX 功率从“12dBm”更新/更改成了“12.5dBm”Go
  • 将 RX 噪声系数从“15dB（76 至 77GHz）”更新/更改成了“14dB（76 至 77GHz）”Go
  • 将 RX 噪声系数从“16dB（77 至 81GHz）”更新/更改成了“15dB（77 至 81GHz）”Go
  • 将 1MHz 时的相位噪声从“–93dBc/Hz（76 至 77GHz）”更新/更改成了“–95dBc/Hz（76 至 77GHz）”Go
  • 将 1MHz 时的相位噪声从“–91dBc/Hz（77 至 81GHz）”更新/更改成了“–93dBc/Hz（77 至 81GHz）”Go
  • 在 “特性”中 将“...物体检测和接口控制”更新/更改成了“物体跟踪、分类和接口控制”Go
  • 在 “特性”中 将“支持晶体...相连接”更新/更改成了“支持 40MHz 晶体...相连接”Go
  • 在“应用”中添加了“人数统计”和 “运动检测”Go
  • 将标题从“自主雷达传感器...”更新/更改成了“汽车传感器”Go
  • 在“器件信息”中添加了托盘器件编号Go
  • 在“器件信息”中将“XI1642QGABL（卷）”更新/更改成了“IWR1642AQAGABLR（卷）”Go
  • 更新了功能框图 中的 RX 和 TX 连接Go
  • 在功能框图 中添加了“射频控制/BIST”框Go
  • Removed "Cascade (20-GHz sync)" from Device Features ComparisonGo
  • Updated/Changed pin B15 to GPIO_41 in Pin DiagramGo
  • Corrected A10 pin to "VOUT_14APLL"Go
  • Updated/Changed pin N14 from "RESERVED" to "DMM_SYNC" in Pin DiagramGo
  • Updated/Changed Pin Attributes (ABL0161 Package) to match the AWR1642 deviceGo
  • Updated/Changed all instances of "CAN_FD_tx" to "Reserved" in Pin Attributes (ABL0161 Package)Go
  • Updated/Changed all instances of "CAN_FD_rx" to "Reserved" in Pin Attributes (ABL0161 Package)Go
  • Added two register tables after Pin AttributesGo
  • Updated/Changed PAD IO Control RegistersGo
  • Cleaned up CLKP and CLKM signals in Signal Descriptions - AnalogGo
  • Removed R14 from Power supply VIOINGo
  • Added pin R15 to Power supply VSSGo
  • Removed duplicate Pin Multiplexing tableGo
  • Updated/Changed all CAN_FD to ReservedGo
  • Cleaned up VIN_13RF1 and VIN_13F2 in Absolute Maximum RatingsGo
  • Updated/Changed CLKP, CLKM row in Absolute Maximum ratings from "Input ports for reference crystal" to "Input ports for reference crystal, or external oscillator input"Go
  • Added table note to ESD RatingsGo
  • Updated/Changed Power-On Hours (POH)Go
  • Added VIN_18VCO row to Recommended Operating ConditionsGo
  • Updated/Changed VIL in Recommended Operating ConditionsGo
  • Updated/Changed VOH MIN from "85% VIOIN" to "VIOIN – 450"Go
  • Updated/Changed VOL MAX from "350" to "450"Go
  • Added NRESET row to Recommended Operating ConditionsGo
  • Updated/Changed Ripple Specifications FREQUENCY from "4200" to "4400"Go
  • Updated Average Power Consumption at Power TerminalsGo
  • Updated/Changed RF Specification to match AWR16Go
  • Updated/Changed IMRR TYP from 40 dB to 21 dBGo
  • Updated/Changed Power Supply Sequencing and Reset Timing imageGo
  • Updated/Changed Clock Specifications text from "(that is, a 40-MHz crystal) " to "(that is, a 40-MHz crystal or external oscillator to CLKP) "Go
  • Updated/Changed Crystal Implementation image from "40 and 50 MHz" to "40 MHz"Go
  • Updated/Changed fP Parallel resonance crystal frequency from " 40, 50" to "40"Go
  • Added External Clock Mode SpecificationsGo
  • Removed External Clock Electrical Characteristics tableGo
  • Updated/Changed External Clock Mode Specifications table to match AWR16Go
  • Updated SPI Slave Mode Switching ParametersGo
  • Updated SPI Slave Mode Timing RequirementsGo
  • Updated/Changed all MIN values in Timing Requirements for QSPI Input (Read) TimingsGo
  • Added "People Counting" and "Gesturing" to Detailed Description OverviewGo
  • Updated/Changed Clock Subsystem diagramGo
  • Updated/Changed Host Interrupt bullet in Host InterfaceGo
  • Removed Security Modules from Master Subsystem, Cortex-R4F Memory MapGo
  • Removed "...and ENOB of ~9 bits" from ADC Channels (Service) for User ApplicationGo
  • Updated/Changed text from "ADC channel mapped to B12" to "GPADC channel 6"Go
  • Updated/Changed GP-ADC Parameter table to match AWR16Go
  • Updated/Changed Monitoring and Diagnostic MechanismsGo
  • Added "People counting", "Gesturing", and "Motion detection" to Application InformationGo
  • Updated/Changed the Device Nomenclature imageGo

3 Device Comparison

Table 3-1 Device Features Comparison

FUNCTION IWR1443 IWR1642
Number of receivers 4 4
Number of transmitters 3 2
On-chip memory 576KB 1.5MB
Max I/F (Intermediate Frequency) (MHz) 15 5
Max real sampling rate (Msps) 37.5 12.5
Max complex sampling rate (Msps) 18.75 6.25
Processor
MCU (R4F) Yes Yes
DSP (C674x) — Yes
Peripherals
Serial Peripheral Interface (SPI) ports 1 2
Quad Serial Peripheral Interface (QSPI) Yes Yes
Inter-Integrated Circuit (I2C) interface 1 1
Controller Area Network (DCAN) interface Yes Yes
Trace — Yes
PWM — Yes
Hardware In Loop (HIL/DMM) — Yes
GPADC Yes Yes
LVDS/Debug Yes Yes
CSI2 Yes —
Hardware accelerator Yes —
1-V bypass mode Yes Yes
JTAG Yes Yes
Product status Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 AI(1) PD(2)
(1) ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

 
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