ZHCSGW1D september   2017  – march 2023 DS90UB953-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended Timing for the Serial Control Bus
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CSI-2 Receiver
        1. 7.3.1.1 CSI-2 Receiver Operating Modes
        2. 7.3.1.2 CSI-2 Receiver High-Speed Mode
        3. 7.3.1.3 CSI-2 Protocol Layer
        4. 7.3.1.4 CSI-2 Short Packet
        5. 7.3.1.5 CSI-2 Long Packet
        6. 7.3.1.6 CSI-2 Errors and Detection
          1. 7.3.1.6.1 CSI-2 ECC Detection and Correction
          2. 7.3.1.6.2 CSI-2 Check Sum Detection
          3. 7.3.1.6.3 D-PHY Error Detection
          4. 7.3.1.6.4 CSI-2 Receiver Status
      2. 7.3.2 FPD-Link III Forward Channel Transmitter
        1. 7.3.2.1 Frame Format
      3. 7.3.3 FPD-Link III Back Channel Receiver
      4. 7.3.4 Serializer Status and Monitoring
        1. 7.3.4.1 Forward Channel Diagnostics
        2. 7.3.4.2 Back Channel Diagnostics
        3. 7.3.4.3 Voltage and Temperature Sensing
          1. 7.3.4.3.1 Programming Example
        4. 7.3.4.4 Built-In Self Test
      5. 7.3.5 FrameSync Operation
        1. 7.3.5.1 External FrameSync
        2. 7.3.5.2 Internally Generated FrameSync
      6. 7.3.6 GPIO Support
        1. 7.3.6.1 GPIO Status
        2. 7.3.6.2 GPIO Input Control
        3. 7.3.6.3 GPIO Output Control
        4. 7.3.6.4 Forward Channel GPIO
        5. 7.3.6.5 Back Channel GPIO
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clocking Modes
        1. 7.4.1.1 Synchronous Mode
        2. 7.4.1.2 Non-Synchronous Clock Mode
        3. 7.4.1.3 Non-Synchronous Internal Mode
        4. 7.4.1.4 DVP Backwards Compatibility Mode
        5. 7.4.1.5 Configuring CLK_OUT
      2. 7.4.2 MODE
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Configuration
        1. 7.5.1.1 CLK_OUT/IDX
          1. 7.5.1.1.1 IDX
      2. 7.5.2 I2C Interface Operation
      3. 7.5.3 I2C Timing
    6. 7.6 Pattern Generation
      1. 7.6.1 Reference Color Bar Pattern
      2. 7.6.2 Fixed Color Patterns
      3. 7.6.3 Packet Generator Programming
        1. 7.6.3.1 Determining Color Bar Size
      4. 7.6.4 Code Example for Pattern Generator
    7. 7.7 Register Maps
      1. 7.7.1  I2C Device ID Register
      2. 7.7.2  Reset
      3. 7.7.3  General Configuration
      4. 7.7.4  Forward Channel Mode Selection
      5. 7.7.5  BC_MODE_SELECT
      6. 7.7.6  PLL Clock Control
      7. 7.7.7  Clock Output Control 0
      8. 7.7.8  Clock Output Control 1
      9. 7.7.9  Back Channel Watchdog Control
      10. 7.7.10 I2C Control 1
      11. 7.7.11 I2C Control 2
      12. 7.7.12 SCL High Time
      13. 7.7.13 SCL Low Time
      14. 7.7.14 Local GPIO DATA
      15. 7.7.15 GPIO Input Control
      16. 7.7.16 DVP_CFG
      17. 7.7.17 DVP_DT
      18. 7.7.18 Force BIST Error
      19. 7.7.19 Remote BIST Control
      20. 7.7.20 Sensor Voltage Gain
      21. 7.7.21 Sensor Control 0
      22. 7.7.22 Sensor Control 1
      23. 7.7.23 Voltage Sensor 0 Thresholds
      24. 7.7.24 Voltage Sensor 1 Thresholds
      25. 7.7.25 Temperature Sensor Thresholds
      26. 7.7.26 CSI-2 Alarm Enable
      27. 7.7.27 Alarm Sense Enable
      28. 7.7.28 Back Channel Alarm Enable
      29. 7.7.29 CSI-2 Polarity Select
      30. 7.7.30 CSI-2 LP Mode Polarity
      31. 7.7.31 CSI-2 High-Speed RX Enable
      32. 7.7.32 CSI-2 Low Power Enable
      33. 7.7.33 CSI-2 Termination Enable
      34. 7.7.34 CSI-2 Packet Header Control
      35. 7.7.35 Back Channel Configuration
      36. 7.7.36 Datapath Control 1
      37. 7.7.37 Remote Partner Capabilities 1
      38. 7.7.38 Partner Deserializer ID
      39. 7.7.39 Target 0 ID
      40. 7.7.40 Target 1 ID
      41. 7.7.41 Target 2 ID
      42. 7.7.42 Target 3 ID
      43. 7.7.43 Target 4 ID
      44. 7.7.44 Target 5 ID
      45. 7.7.45 Target 6 ID
      46. 7.7.46 Target 7 ID
      47. 7.7.47 Target 0 Alias
      48. 7.7.48 Target 1 Alias
      49. 7.7.49 Target 2 Alias
      50. 7.7.50 Target 3 Alias
      51. 7.7.51 Target 4 Alias
      52. 7.7.52 Target 5 Alias
      53. 7.7.53 Target 6 Alias
      54. 7.7.54 Target 7 Alias
      55. 7.7.55 Back Channel Control
      56. 7.7.56 Revision ID
      57. 7.7.57 Device Status
      58. 7.7.58 General Status
      59. 7.7.59 GPIO Pin Status
      60. 7.7.60 BIST Error Count
      61. 7.7.61 CRC Error Count 1
      62. 7.7.62 CRC Error Count 2
      63. 7.7.63 Sensor Status
      64. 7.7.64 Sensor V0
      65. 7.7.65 Sensor V1
      66. 7.7.66 Sensor T
      67. 7.7.67 CSI-2 Error Count
      68. 7.7.68 CSI-2 Error Status
      69. 7.7.69 CSI-2 Errors Data Lanes 0 and 1
      70. 7.7.70 CSI-2 Errors Data Lanes 2 and 3
      71. 7.7.71 CSI-2 Errors Clock Lane
      72. 7.7.72 CSI-2 Packet Header Data
      73. 7.7.73 Packet Header Word Count 0
      74. 7.7.74 Packet Header Word Count 1
      75. 7.7.75 CSI-2 ECC
      76. 7.7.76 IND_ACC_CTL
      77. 7.7.77 IND_ACC_ADDR
      78. 7.7.78 IND_ACC_DATA
      79. 7.7.79 FPD3_TX_ID0
      80. 7.7.80 FPD3_TX_ID1
      81. 7.7.81 FPD3_TX_ID2
      82. 7.7.82 FPD3_TX_ID3
      83. 7.7.83 FPD3_TX_ID4
      84. 7.7.84 FPD3_TX_ID5
      85. 7.7.85 Indirect Access Registers
        1. 7.7.85.1  PGEN_CTL
        2. 7.7.85.2  PGEN_CFG
        3. 7.7.85.3  PGEN_CSI_DI
        4. 7.7.85.4  PGEN_LINE_SIZE1
        5. 7.7.85.5  PGEN_LINE_SIZE0
        6. 7.7.85.6  PGEN_BAR_SIZE1
        7. 7.7.85.7  PGEN_BAR_SIZE0
        8. 7.7.85.8  PGEN_ACT_LPF1
        9. 7.7.85.9  PGEN_ACT_LPF0
        10. 7.7.85.10 PGEN_TOT_LPF1
        11. 7.7.85.11 PGEN_TOT_LPF0
        12. 7.7.85.12 PGEN_LINE_PD1
        13. 7.7.85.13 PGEN_LINE_PD0
        14. 7.7.85.14 PGEN_VBP
        15. 7.7.85.15 PGEN_VFP
        16. 7.7.85.16 PGEN_COLOR0
        17. 7.7.85.17 PGEN_COLOR1
        18. 7.7.85.18 PGEN_COLOR2
        19. 7.7.85.19 PGEN_COLOR3
        20. 7.7.85.20 PGEN_COLOR4
        21. 7.7.85.21 PGEN_COLOR5
        22. 7.7.85.22 PGEN_COLOR6
        23. 7.7.85.23 PGEN_COLOR7
        24. 7.7.85.24 PGEN_COLOR8
        25. 7.7.85.25 PGEN_COLOR9
        26. 7.7.85.26 PGEN_COLOR10
        27. 7.7.85.27 PGEN_COLOR11
        28. 7.7.85.28 PGEN_COLOR12
        29. 7.7.85.29 PGEN_COLOR13
        30. 7.7.85.30 PGEN_COLOR14
        31. 7.7.85.31 PGEN_COLOR15
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power-over-Coax
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 CSI-2 Interface
        2. 8.2.2.2 FPD-Link III Input / Output
        3. 8.2.2.3 Internal Regulator Bypassing
        4. 8.2.2.4 Loop Filter Decoupling
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequencing
      1. 9.1.1 System Initialization
    2. 9.2 Power Down (PDB)
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CSI-2 Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

4 Revision History

Changes from Revision C (October 2020) to Revision D (March 2023)

  • 更新了首页上的典型功耗要点以匹配电气特性表Go
  • IDD_TOTAL typical value changed to 160 mAGo
  • Changed I2C terminology to "Controller" and "Target"Go
  • Removed extra arrow from DPHY Receiver to Clock Gen blocks in Functional Block DiagramGo
  • Added description for non-continuous clock lane modeGo
  • Added description for deserializer SENSOR_STS registersGo
  • Updated script example for voltage monitoringGo
  • Updated description for reading GPIO status when set as output and added GPIO Configuration tableGo
  • Added information for enabling Forward Channel GPIO using FC_GPIO_ENGo
  • Updated GPIO Output Control section description for enabling register 0x0EGo
  • Added typical latency to Forward Channel GPIO tableGo
  • Updated Clocking Mode table with additional modes, frequency clarifications, and CSI-2 bandwidth clarificationsGo
  • Corrected effect of setting M value in register 0x06 Go
  • Updated description to refer to "DVP_DT_MATCH_EN" in register 0x11. Go
  • Changed 0x17[7:4] default value from 0x0 to 0x3Go
  • Added max and min readings to Voltage Sensor Thresholds description in Register 0x19 Go
  • Updated SENSOR_V1_THRESH description to match SENSOR_V0_THRESH in register 0x1AGo
  • Changed "GPIO0 Sensor" to "Internal Temperature Sensor" in register 0x57Go
  • Changed "FPD3_RX_ID" to "FPD3_TX_ID" in registers 0xF0-0xF5Go
  • Changed PoC network impedance recommendation from 2 kΩ to 1 kΩGo
  • Updated PoC descriptionGo
  • Removed IL and RL values from Suggested Characteristics for Single-Ended PCB Traces With Attached PoC Networks TableGo
  • Changed FB1-FB3 requirement to DCR < 500 mΩ.Go
  • Added note for setting watchdog timer for system initializationGo
  • Corrected PDB capacitor from 1-μF to 10-μFGo

Changes from Revision B (September 2018) to Revision C (October 2020)

  • 新增了特性要点“提供功能安全型”Go

Changes from Revision A (February 2018) to Revision B (September 2018)

  • Updated GPIO pin descriptions. Go
  • Replace CLK_IN with clock throughout document. Go
  • Changed Supply voltage from 2.5V to 2.16VGo
  • Changed asynchronous to non-synchronousGo
  • Deleted "for synchronous mode"Go
  • Added internal reference frequency in EC tableGo
  • Added Internal AON Clock to Block Diagram.Go
  • Changed mode to modes. Go
  • Changed 130ns to 225ns.Go
  • Changed latency to 1.5us and jitter to 0.7us. Go
  • Changed CLK_IN Mode to Modes. Go
  • Added DVP Mode Go
  • Changed table formatting. Go
  • Changed REFLCK to Back Channel Go
  • Added Frequency for Synchronous Mode Go
  • Changed naming convention from "asynchronous CLK_IN" to "Non-Synchronous external CLK_IN" mode column dor CLKIN_DIV = 2Go
  • Added Non-Synchronous Internal Clock Mode Go
  • Changed the value from 24.2 - 25.5 MHz to 48.4 - 51 MHz Go
  • Changed the value from 25 - 52 MHz to 24.2 to 25.5 MHz Go
  • Added DVP External Clock.Go
  • Added text "Deserializer Mode" to clarify mode RAW10 Go
  • Added text "Deserializer Mode" to clarify mode RAW12 HF Go
  • Added additional information to note. Go
  • Added Added Footnote for Local Reference Source Go
  • Changed CLK_IN to Clock.Go
  • Added Non-Synchronous Internal Clocking Mode section. Go
  • Changed the internal clock 25 MHz to 24.2 MHz Go
  • Changed forward channel rate to1.936 Gbps instead of 2 Gbps Go
  • Changed the average CSI-2 throughput value to 3.1 Gbps instead of 1.6 Gbps Go
  • Added DVP Backwards Compatibility Mode section.Go
  • Changed "asynchronous CLK_IN" to "Non-Synchronous external CLK_IN"Go
  • Added sentence "CLK_OUT functionality is not..."Go
  • Added Non-Synchronous Internal Clock Mode Go
  • Deleted "with accuracy of 25 MHz ±10%.Go
  • Changed clock to from 25 MHz ±10% to 26.25 MHz. Go
  • Changed clock to from 25 MHz ±10% to 26.25 MHz. Go
  • Updated registers map Go
  • Added information for DVP mode to register 0x04. Go
  • Added "operating with Non-Synchronous internal clock or"Go
  • Added "operating with Non-Synchronous internal clock or"Go
  • Changed the frequency value from 26 MHz to range value (24.2 MHz to 25.5 MHz) Go
  • Added "set for 2 Gbps line rate" Go
  • Changed the frequency value from 52 MHz to range value (48.4 MHz to 51 MHz) Go
  • Added "set for 4 Gbps line rate" in register 0x05 Go
  • Updated unit time and clock frequency. Go
  • Added DVP information to register 0x10. Go
  • Added DVP information to register 0x11. Go
  • Deleted the value -25dB and added -20dB in typcial Go
  • Changed –26.4+14.4f to log equation –12+8*log(f) Go
  • Moved Return Loss, S11 MAX values to TYPGo
  • Added Typical connection diagram for STP Go
  • Changed the capacitance value from 33nF to 33nF – 100 nF. Go
  • Changed the capacitance value from 15 nF to 15 nF – 47 nF.Go
  • Changed the capacitance value from 33nF to 33nF – 100 nF. Go

Changes from Revision * (September 2017) to Revision A (December 2017)

  • 新增了特性要点“提供功能安全型”Go
  • Changed RES1 pin description from "Leave OPEN" to "Do not connect" Go
  • Added "Internal 1-MΩ pulldown" text to PDB pin descriptionGo
  • Expanded MODE pin description Go
  • Changed "Requires" to "Typically connected to" in the Power and Ground pin descriptions Go
  • Changed "and should not be connected to an external supply" to "Do not connect to an external supply rail" in the Power and Ground pin descriptions Go
  • Changed the CSI_ERR_COUNT (0x5C) text to CSI_ERR_CNT (0x5C)Go
  • Changed DS90UBUB954-Q1 to DS90UB954-Q1Go
  • Changed the GPIO_INPUT_CTL text to GPIO_INPUT_CTRL in the GPIO Input Control and GPIO Output Control sectionsGo
  • Changed CLK_IN lower limit with CLKIN_DIV =1 from 46 MHz to 25 MHz and CLK_IN lower limit from 92 MHz to 50 MHz.Go
  • Corrected typo in MODE description saying the number of modes is 3 to the correct value of 2Go
  • Changed I2C START description to "A START occurs when SDA transitions Low while SCLK is High" Go
  • Added sentence and table to clarify reserved registers Go
  • Added registers tables for reserved registers 0x04, 0x0F-0x12, 0x16, 0x1F, 0x25-0x30, 0x34, 0x36, 0x38, 0x4A-0x4F, 0x5B, 0x65-0xAF, and 0xB3-0xEF.Go
  • Changed bit 6 and bit 7 in the MODE_SEL register to RESERVEDGo
  • Changed the SENSE_VO_HI and SENSE_VO_LO registers to SENSE_V0_HI and SENSE_V0_LO to match the title in Table 7-34 Go
  • Changed the SENSE_V0_HI and SENSE_V0_LO bit descriptionsGo
  • Changed the SENSOR_V0_THRESH bit description Go
  • Changed the SENSE_T_HI and SENSE_T_LO bit descriptionsGo
  • Combined the CSI_EN_HSRX register bits 6–0 into one rowGo
  • Combined the CSI_EN_LPRX register bits 6–0 into one rowGo
  • Combined the CSI_EN_RXTERM register bits 7–4 into one rowGo
  • Changed serializer to deserializer in TARGET_ID_ALIAS_x bit descriptions Go
  • Changed Target 0 to Target 1 in the TARGET_AUTO_ACK_1 bit descriptionGo
  • Changed Target 0 to Target 2 in the TARGET_AUTO_ACK_2 bit descriptionGo
  • Changed Target 0 to Target 3 in the TARGET_AUTO_ACK_3 bit descriptionGo
  • Changed Target 0 to Target 4 in the TARGET_AUTO_ACK_4 bit descriptionGo
  • Changed Target 0 to Target 5 in the TARGET_AUTO_ACK_5 bit descriptionGo
  • Changed Target 0 to Target 6 in the TARGET_AUTO_ACK_6 bit descriptionGo
  • Changed Target 0 to Target 7 in the TARGET_AUTO_ACK_7 bit descriptionGo
  • Changed CRC_ERR bit description in GENERAL_STATUS to match CRC_ERR_CLR register name Go
  • Changed the CNTRL_ERR_HSRQST_2 bit descriptionGo
  • Changed Typical Applications Coaxial Diagram captionGo
  • Added PIN(S) column to Table 8-3 Go
  • Changed large bulk capacitor typical range lower limit from 50 µF to 47 µF, removed mentions of dedicated power plane and tantalum capacitors, and changed recommended power rating for capacitors in layout guidelines Go
  • Changed recommended CSI-2 guidelines on matching trace lengths and routing to help trace impedanceGo
  • Changed routing guidelines for the DOUT+ and DOUT– pins Go
  • Added new links to the Related Documentation sectionGo