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  • CDCI6214 超低功耗时钟发生器（具有 PCIe 支持、四路可编程输出和 EEPROM）

    • ZHCSGV7F July   2017  – January 2024 CDCI6214

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  • CDCI6214 超低功耗时钟发生器（具有 PCIe 支持、四路可编程输出和 EEPROM）
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  EEPROM Characteristics
    6. 6.6  Reference Input, Single-Ended and Differential Mode Characteristics (REFP, REFN, FB_P, FB_N)
    7. 6.7  Reference Input, Crystal Mode Characteristics (XIN, XOUT)
    8. 6.8  General-Purpose Input and Output Characteristics (GPIO[4:1], SYNC/RESETN)
    9. 6.9  Triple Level Input Characteristics (EEPROMSEL, REFSEL)
    10. 6.10 Reference Mux Characteristics
    11. 6.11 Phase-Locked Loop Characteristics
    12. 6.12 Closed-Loop Output Jitter Characteristics
    13. 6.13 Output Mux Characteristics
    14. 6.14 LVCMOS Output Characteristics
    15. 6.15 HCSL Output Characteristics
    16. 6.16 LVDS DC-Coupled Output Characteristics
    17. 6.17 Programmable Differential AC-Coupled Output Characteristics
    18. 6.18 Output Skew and Delay Characteristics
    19. 6.19 Output Synchronization Characteristics
    20. 6.20 Timing Characteristics
    21. 6.21 I2C-Compatible Serial Interface Characteristics (SDA/GPIO2, SCL/GPIO3)
    22. 6.22 Timing Requirements, I2C-Compatible Serial Interface (SDA/GPIO2, SCL/GPIO3)
    23. 6.23 Power Supply Characteristics
    24. 6.24 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Parameters
      1. 7.1.1 Reference Inputs
      2. 7.1.2 Outputs
      3. 7.1.3 Serial Interface
      4. 7.1.4 Power Supply
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference Block
        1. 8.3.1.1 Input Stages
          1. 8.3.1.1.1 Crystal Oscillator
          2. 8.3.1.1.2 LVCMOS
          3. 8.3.1.1.3 Differential AC-Coupled
        2. 8.3.1.2 Reference Mux
        3. 8.3.1.3 Reference Divider
          1. 8.3.1.3.1 Doubler
        4. 8.3.1.4 Bypass-Mux
        5. 8.3.1.5 Zero Delay, Internal and External Path
      2. 8.3.2 Phase-Locked Loop
      3. 8.3.3 Clock Distribution
        1. 8.3.3.1 Output Channel
        2. 8.3.3.2 Divider Glitch-Less Update
      4. 8.3.4 Control Pins
        1. 8.3.4.1 Global and Individual Output Enable: OE and OE_Y[4:1]
      5. 8.3.5 Operation Modes
      6. 8.3.6 Divider Synchronization - SYNC
      7. 8.3.7 EEPROM - Cyclic Redundancy Check
      8. 8.3.8 Power Supplies
        1. 8.3.8.1 Power Management
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Mode
      2. 8.4.2 Serial Interface Mode
        1. 8.4.2.1 Fall-Back Mode
    5. 8.5 Programming
      1. 8.5.1 Recommended Programming Procedure
      2. 8.5.2 EEPROM Access
      3. 8.5.3 Device Defaults
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Setup
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Power-Up Sequence
      2. 9.5.2 De-Coupling
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Examples
  11. 10Register Maps
    1. 10.1 CDCI6214 Registers
    2. 10.2 EEPROM Map
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Device Nomenclature
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
  15. 重要声明
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Data Sheet

CDCI6214 超低功耗时钟发生器（具有 PCIe 支持、四路可编程输出和 EEPROM）

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 一个可配置的高性能低功耗 PLL，具有 4 路可编程输出
  • RMS 抖动性能
    • 支持不带 SSC 的第 1/2/3/4 代 PCIe
  • 典型功耗：1.8V 时为 150mW(2)
  • 通用时钟输入
    • 差分交流耦合或 LVCMOS：1MHz 至 250MHz
    • 晶振：8MHz 至 50MHz
  • 灵活输出频率
    • 44.1kHz 至 350MHz
    • 无毛刺输出分频器切换
  • 四路可独立配置的输出
    • LVCMOS、LVDS 或 HCSL 输出
    • 具有可编程摆幅的差分交流耦合输出（与 LVDS、CML-、LVPECL 兼容）
  • 完全集成的 PLL，可配置的环路带宽：100kHz 至 3MHz
  • 通过单电源或混合电源供电进行电平转换：1.8V、2.5V 和 3.3V
  • 可配置 GPIO
    • 状态信号
    • 最多 4 个独立输出使能端子
    • 输出分频器同步
  • 灵活的配置选项
    • 兼容 I2C 的接口：频率高达 400kHz
    • 具有两个页面和外部选择引脚的集成 EEPROM
  • 仅支持 100Ω 系统
  • 工业温度范围：–40°C 至 85°C
  • 小尺寸：24 引脚 VQFN (4mm × 4mm)

2 应用

  • PCIe 第 1/2/3/4 代时钟
  • 1G/10G 以太网交换机、NIC、加速器
  • 测试和测量、手持设备
  • 多功能打印机
  • 广播基础设施

3 说明

CDCI6214 器件是一款超低功耗时钟发生器。此器件在锁相环的两个独立基准输入之间进行选择，并在可配置的差分输出通道上产生多达四个不同的频率，还在 LVCMOS 输出通道上生成参考时钟。

四个输出通道中的每个通道都有一个可配置的整数分频器。通过与输出多路复用器结合，这样可产生五种不同的频率。时钟分配分频器通过确定性方式进行复位，以便实现干净的时钟门控以及无毛刺更新功能。可通过灵活的断电选项优化器件以便在工作和待机模式中实现最低功耗。通常，四路 156.25MHz LVDS 输出在 1.8V 时的功耗为 150mW。100MHz HCSL 输出的典型 RMS 抖动为 386fs，可提高 PCIe 应用的系统裕度。

CDCI6214 由内部寄存器进行配置。可通过与 I2C 兼容的串行接口和内部 EEPROM 访问这些寄存器。

CDCI6214 采用小型封装并具有超低功耗，可根据单个基准实现高性能时钟树。CDCI6214 具有工厂和用户可编程的 EEPROM，该时钟特性方便易用，可瞬时启动，并能实现低功耗。

封装信息
器件型号 封装(1) 封装尺寸(3)
CDCI6214 RGE（VQFN，24） 4.00mm x 4.00mm
(1) 有关所有可选封装，请参阅 节 13。
(2) 四路 LVDS 输出，156.25MHz（含晶振参考）。
(3) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。
GUID-12A151EB-A070-4389-B78F-E3FCC3CE01D3-low.gif CDCI6214 应用示例

4 Device Comparison

Table 4-1 Device Comparison
IDENTIFIER REFERENCE INPUTS ORDERABLE PART NUMBER CHANNEL DIVIDER CLOCK
OUTPUTS		 GENERAL-PURPOSE PINS OUTPUT POWER SUPPLY PINS
CDCI6214 2 CDCI6214RGER Integer 4 + 1 4 2
CDCI6214-Q1 2 CDCI6214TRGERQ1 Integer 4 + 1 4 2
CDCI6212 2 CDCI6212RGER Integer 2 + 1 2 2

5 Pin Configuration and Functions

GUID-E5D29B91-BF39-42B6-A9F3-1CE99E0473D1-low.gifFigure 5-1 RGE Package24-Pin VQFNTop View
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
XOUT/FB_P 1 IO Crystal Driver Output / LVCMOS Input / Differential Positive Reference
XIN/FB_N 2 I Crystal Input / Differential Negative Reference
VDDREF 3 P Power Supply Pin for Input Path, Digital and EEPROM
REFSEL 4 I Manual Reference Selection MUX for PLL, RPU = 50 kΩ, RPD = 50 kΩ
REFP 5 I Differential Positive Reference
REFN 6 I Differential Negative Reference
Y0 7 O Output 0 Pin
RESETN/SYNC 8 I Chip Reset. Alternatively, Output Divider Sync, RPU = 50 kΩ(1)
Y4N 9 O Output 4 Negative Pin
Y4P 10 O Output 4 Positive Pin
OE/GPIO4 11 IO Global output enable (default) or programmable GPIO, RPU = 50 kΩ(1)
SCL/GPIO3 12 IO Serial interface clock (default) or programmable GPIO
Y3N 13 O Output 3 Negative Pin
Y3P 14 O Output 3 Positive Pin
VDDO34 15 P Power Supply for Outputs 3 and 4
VDDO12 16 P Power Supply for Outputs 1 and 2
Y2N 17 O Output 2 Negative Pin
Y2P 18 O Output 2 Positive Pin
SDA/GPIO2 19 IO Serial interface data (default) or programmable GPIO
STATUS/GPIO1 20 IO Status (default) or programmable GPIO, RPU = 50 kΩ(1)
Y1N 21 O Output 1 Negative Pin
Y1P 22 O Output 1 Positive Pin
EEPROMSEL 23 I EEPROM Page Mode Select, RPU = 50 kΩ, RPD = 50 kΩ(1)
VDDVCO 24 P Power Supply Pin for VCO / PLL
GND 25 G Ground, Thermal Pad
(1) RPU is an internal pullup resistor. RPD is an internal pulldown resistor.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
VDDREF, VDDVCO, VDDO12, VDDO34Supply voltage–0.33.65V
XIN/FB_P, XOUT/FB_N, REFP, REFNInput voltage–0.3VDDREF + 0.3V
STATUS/GPIO1, SDA/GPIO2, SCL/GPIO3, OE/GPIO4, REFSEL, EEPROMSEL, RESETN/SYNCInput voltage–0.3VDDREF + 0.3V
Y0, Y1P, Y1N, Y2P, Y2N, Y3P, Y3N, Y4P, Y4NOutput voltage–0.3VDDO_x + 0.3V
STATUS/GPIO1, SDA/GPIO2, SCL/GPIO3, OE/GPIO4Output voltage–0.3VDDREF + 0.3V
TJJunction temperature125°C
TstgStorage temperature150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

 
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