INA165x-Q1 SoundPlus™ 高共模抑制线路接收器
- ZHCSGP4C August 2017 – May 2019 INA1650-Q1 , INA1651-Q1
  
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INA165x-Q1 SoundPlus™ 高共模抑制线路接收器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

符合面向汽车应用的 AEC-Q100 标准
- 温度等级 1：–40°C 至 +125°C，T_A
高共模抑制：91dB（典型值）
高输入阻抗：1MΩ 差分
超低噪声：-104.7dBu，未加权
超低总谐波失真 + 噪声：
-119dB THD+N（20dBu，22kHz 带宽）
短路保护
集成电磁干扰 (EMI) 滤波器
宽电源电压范围：±2.25V 至 ±12V
采用小型 14 引脚 TSSOP 封装

2 应用

车厢麦克风前置放大器
信息娱乐系统
音频输入电路
线路驱动器
外部音频功率放大器

简化内部原理图

INA1650-Q1 INA1651-Q1 ina1650_1-Q1-simplified-internal-schematic.gif

3 说明

INA1650-Q1 双通道和 INA1651-Q1 单通道 (INA165x-Q1) SoundPlus™音频线路接收器可实现 91dB 的极高共模抑制比 (CMRR)，与此同时，对于 20dBu 信号电平，可在 1kHz 时保持 -119dB 的超低 THD+N。不同于其他线路接收器产品，INA165x-Q1 CMRR 在额定温度范围内能保持特性不变，经生产测试，可在各种应用中提供稳定的性能。

INA165x-Q1 器件支持 ±2.25V 至 ±12V 的极宽电源电压范围。除线路接收器通道以外，INA165x-Q1 还包含一个缓冲 1/2 Vs 基准输出，因此可配置为用于双电源或单电源应用。1/2 Vs 输出可用作信号链中的另一个模拟电路的偏置电压。

INA1650-Q1 具有独特的内部布局，即使在过驱或过载条件下也可在通道间实现最低串扰和零交互。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
INA1650-Q1	TSSOP (14)	5.00mm × 4.40mm
INA1651-Q1	TSSOP (14)	5.00mm × 4.40mm

如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

CMRR 直方图（5746 通道）

4 修订历史记录

Changes from B Revision (April 2019) to C Revision

Changed ESD Ratings table to show individual device ratings Go

Changes from A Revision (October 2017) to B Revision

Added 向数据表中添加了 INA1651-Q1 器件和相关内容Go

Changes from * Revision (August 2017) to A Revision

INA1650-Q1 的建议电源电压范围从 36V 降到了 24V。文本、图表和电路图中提及的所有 36V 工作电压都已删除或修改，以反映 24V 的最大电源电压。Go

5 Pin Configuration and Functions

INA1650-Q1 PW Package

14-Pin TSSOP

Top View

Pin Functions: INA1650-Q1

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
COM A	3	I	Input common, channel A
COM B	6	I	Input common, channel B
IN+ A	2	I	Noninverting input, channel A
IN– A	4	I	Inverting input, channel A
IN+ B	7	I	Noninverting input, channel B
IN– B	5	I	Inverting input, channel B
OUT A	13	O	Output, channel A
OUT B	8	O	Output, channel B
REF A	12	I	Reference input, channel A. This pin must be driven from a low impedance.
REF B	9	I	Reference input, channel B. This pin must be driven from a low impedance.
VCC	1	—	Positive (highest) power supply
VEE	14	—	Negative (lowest) power supply
VMID(IN)	11	I	Input node of internal supply divider. Connect a capacitor to this pin to reduce noise from the supply divider circuit.
VMID(OUT)	10	O	Buffered output of internal supply divider.

INA1651-Q1 PW Package

14-Pin TSSOP

Top View

Pin Functions: INA1651-Q1

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
COM A	3	I	Input common, channel A
IN+ A	2	I	Noninverting input, channel A
IN– A	4	I	Inverting input, channel A
NC	5	—	No internal connection
NC	6	—	No internal connection
NC	7	—	No internal connection
NC	8	—	No internal connection
NC	9	—	No internal connection
OUT A	13	O	Output, channel A
REF A	12	I	Reference input, channel A. This pin must be driven from a low impedance.
VCC	1	—	Positive (highest) power supply
VEE	14	—	Negative (lowest) power supply
VMID(IN)	11	I	Input node of internal supply divider. Connect a capacitor to this pin to reduce noise from the supply divider circuit.
VMID(OUT)	10	O	Buffered output of internal supply divider.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	Supply voltage, V_S = (V+) – (V–)		40	V
	Input voltage (signal inputs, enable, ground)	(V–) – 0.5	(V+) + 0.5
	Input differential voltage		(V+) – (V–)
Current	Input current (all pins except power-supply pins)		±10	mA
Current	Output short-circuit⁽²⁾	Continuous
Temperature	Operating, T_A	–55	125	°C
	Junction, T_J		150
	Storage, T_stg	–65	150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Short-circuit to V_S / 2 (ground in symmetrical dual supply setups), one amplifier per package.

6.2 ESD Ratings

			VALUE	UNIT
INA1650-Q1
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾ HBM ESD Classification Level 3A	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011 CDM ESD Classification Level C6	±1000	V
INA1651-Q1
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾ HBM ESD Classification Level 2	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4A	±500	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	NOM	MAX	UNIT
Supply voltage (V+ – V–)	4.5 (±2.25)		24 (±12)	V
Specified temperature	–40		125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		INA1650-Q1	INA1651-Q1	UNIT
		PW (TSSOP)	PW (TSSOP)
		14 PINS	14 PINS
R_θJA	Junction-to-ambient thermal resistance	97.0	99.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	22.6	29.9	°C/W
R_θJB	Junction-to-board thermal resistance	40.4	42.6	°C/W
ψ_JT	Junction-to-top characterization parameter	0.9	1.5	°C/W
ψ_JB	Junction-to-board characterization parameter	39.6	42.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics:

at T_A = 25°C, V_S = ±2.25 V to ±12 V, V_CM = V_OUT = midsupply, and R_L = 2 kΩ (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
AUDIO PERFORMANCE
THD+N	Total harmonic distortion + noise	V_O = 3 V_RMS, f = 1kHz, 90-kHz measurement bandwidth, V_S = ±12 V			0.00039%
					–108.1		dB
		V_IN = 20 dBu (7.746 V_RMS) , F_IN = 1 kHz, V_S = ±12 V, 90-kHz measurement bandwidth			0.000224%
					–113.0		dB
IMD	Intermodulation distortion	SMPTE and DIN two-tone, 4:1 (60 Hz and 7 kHz) V_O = 3 V_RMS, 90-kHz measurement bandwidth			0.0005%
					–106.1		dB
		CCIF twin-tone (19 kHz and 20 kHz), V_O = 3 V_RMS, 90-kHz measurement bandwidth			0.00066%
					–103.6		dB
AC PERFORMANCE
BW	Small-signal bandwidth				2.7		MHz
SR	Slew rate				10		V/μs
	Full-power bandwidth⁽¹⁾	V_O = 1 V_P			1.59		MHz
PM	Phase margin	C_L = 20 pF			71		degrees
PM	Phase margin	C_L = 200 pF			54		degrees
t_s	Settling time	To 0.01%, V_s = ±12 V, 10-V step			2.2		μs
	Overload recovery time				330		ns
	Channel separation	f = 1 kHz, REF and COM pins connected to ground			140		dB
	Channel separation	f = 1 kHz, REF and COM pins connected to VMID(OUT)			130		dB
	EMI/RFI filter corner frequency				80		MHz
NOISE
	Output voltage noise	f = 20 Hz to 20 kHz, no weighting			4.5		μV_RMS
	Output voltage noise	f = 20 Hz to 20 kHz, no weighting			–104.7		dBu
e_n	Output voltage noise density⁽²⁾	f = 100 Hz			47		nV/√Hz
e_n	Output voltage noise density⁽²⁾	f = 1 kHz			31		nV/√Hz
OFFSET VOLTAGE
V_OS	Output offset voltage				±1	±3	mV
V_OS	Output offset voltage	T_A = –40°C to 125°C⁽²⁾				±4	mV
dV_OS/dT	Output offset voltage drift⁽²⁾	T_A = –40°C to 125°C			2	7	μV/°C
PSRR	Power-supply rejection ratio				2		μV/V
GAIN
	Gain				1		V/V
	Gain error				0.04%	0.05%
	Gain error	T_A = –40°C to 125°C⁽²⁾			0.05%	0.06%
	Gain nonlinearity	V_S = ±12 V, –10 V < V_O < 10 V ⁽²⁾			1	5	ppm
INPUT VOLTAGE
V_CM	Common-mode voltage			(V–) + 0.25		(V+) – 2	V
CMRR	Common-mode rejection ratio	(V–) + 0.25 V ≤ V_CM ≤ (V+) – 2 V, REF and COM pins connected to ground, V_S = ±12 V		85	91		dB
		T_A = –40°C to 125°C⁽²⁾		82	89
		(V–) + 0.25 V ≤ V_CM ≤ (V+) – 2 V, REF and COM pins connected to VMID(OUT), V_S = ±12 V		82	86
		T_A = –40°C to 125°C⁽²⁾		76	84
CMRR	Common-mode rejection ratio	(V–) + 0.25 V ≤ V_CM ≤ (V+) – 2 V, REF and COM pins connected to ground, V_S = ±12 V, R_S mismatch = 20 Ω			84		dB
INPUT IMPEDANCE
	Differential			850	1000	1150	kΩ
	Common-mode			212.5	250	287.5	kΩ
	Input resistance mismatch				0.01%	0.25%
SUPPLY DIVIDER CIRCUIT
	Nominal output voltage				[(V+) + (V–)] / 2		V
	Output voltage offset	VMID(IN) = ((V+) + (V–) / 2			2	4	mV
	Input impedance	VMID(IN) pin, f = 1 kHz			250		kΩ
	Output resistance	VMID(OUT) pin			0.35		Ω
	Output voltage noise	20 Hz to 20 kHz, C_MID = 1 µF			1.56		µV_RMS
	Output capacitive load limit	Phase Margin > 45°, R_ISO = 0 Ω			150		pF
OUTPUT
V_O	Voltage output swing from rail	Positive rail	R_L = 2 kΩ		350		mV
		Positive rail	R_L = 600 Ω		1100
		Negative rail	R_L = 2 kΩ		430
		Negative rail	R_L = 600 Ω		1300
Z_OUT	Output impedance	f ≤ 100 kHz, I_OUT = 0 A			< 1		Ω
I_SC	Short-circuit current	V_S = ±12 V			±75		mA
C_LOAD	Capacitive load drive			See Figure 19			pF
POWER SUPPLY
I_Q	Quiescent current	I_OUT = 0 A, INA1651-Q1		4.6	6	6.9	mA
		I_OUT = 0 A, INA1651-Q1	T_A = –40°C to 125°C⁽²⁾			8
		I_OUT = 0 A, INA1650-Q1		8	10.5	12
		I_OUT = 0 A, INA1650-Q1	T_A = –40°C to 125°C⁽²⁾			14

(1) Full-power bandwidth = SR / (2π × V_P), where SR = slew rate.

(2) Specified by design and characterization.

6.6 Typical Characteristics

at T_A = 25°C, V_S = ±12 V, V_CM = V_OUT = midsupply, and R_L = 2 kΩ (unless otherwise noted)

5746 channels

V_REF pins connected to ground

Figure 1. Common-Mode Rejection Ratio Distribution

5746 channels

Figure 3. Distribution of Mismatch in 500-kΩ Input Resistors

5746 channels

Figure 5. Offset Voltage Distribution

Figure 7. Frequency Response

Figure 9. Common-Mode Rejection Ratio vs Frequency

Figure 11. Voltage Noise Spectral Density

3 V_RMS, 500-kHz measurement bandwidth

Figure 13. THD+N vs Frequency

INA1650-Q1 INA1651-Q1 new_C104_SBOS772.png

SMPTE 4:1 60 Hz and 7 kHz, 90-kHz measurement bandwidth

Figure 15. SMPTE Intermodulation Distortion vs Output Amplitude

Figure 17. Signal Path Output Impedance vs Frequency

100-mV input step

Figure 19. Overshoot vs Capacitive Load

10-mV input step

Figure 21. Small-Signal Step Response

10-V input step, 0.01% settling = ±1 mV

Figure 23. Rising-Edge Settling Time

INA1650-Q1 INA1651-Q1 new_C306_SBOS772.png

Figure 25. No Phase Reversal

INA1650-Q1 INA1651-Q1 new_C019_SBOS772.png

5 typical units

Figure 27. Output Offset Voltage vs Common-Mode Voltage

INA1650-Q1 INA1651-Q1 new_C007_SBOS772.png

Figure 29. Positive Output Voltage vs Output Current

INA1650-Q1 INA1651-Q1 new_C005_SBOS772.png

Figure 31. Quiescent Current vs Power Supply Voltage

INA1650-Q1 INA1651-Q1 new_ai_C006_SBOS772.png

REF A/B connected to 0 V

Figure 33. Input Common-Mode Voltage vs Output Voltage

INA1650-Q1 INA1651-Q1 ai_C008_SBOS818.png

REF A/B connected to VMID(OUT)

Figure 35. Input Common-Mode Voltage vs Output Voltage

INA1650-Q1 INA1651-Q1 ai_C010_SBOS818.png

REF A/B connected to 0 V

Figure 37. Input Common-Mode Voltage vs Output Voltage

5746 channels

V_REF pins connected to V_MID(OUT)

Figure 2. Common-Mode Rejection Ratio Distribution

5746 channels

Figure 4. Gain Error Distribution

52 channels

Figure 6. Offset Voltage Drift Distribution

INA1650-Q1 INA1651-Q1 new_C001_SBOS772.png

Figure 8. Maximum Output Voltage vs Frequency

Figure 10. Power Supply Rejection Ratio vs Frequency

3 V_RMS, 90-kHz measurement bandwidth

Figure 12. THD+N vs Frequency

INA1650-Q1 INA1651-Q1 new_C103_SBOS772.png

1 kHz, 90-kHz measurement bandwidth

Figure 14. THD+N vs Output Amplitude

INA1650-Q1 INA1651-Q1 new_C105_SBOS772.png

CCIF 19 kHz and 20 kHz, 90-kHz measurement bandwidth

Figure 16. CCIF Intermodulation Distortion vs Output Amplitude

C_F = 1 µF

Figure 18. Supply Divider Output Impedance vs Frequency

Figure 20. Channel Separation vs Frequency

10-V input step

Figure 22. Large-Signal Step Response

10-V input step, 0.01% settling = ±1 mV

Figure 24. Falling-Edge Settling Time

5 typical units

Figure 26. CMRR vs Temperature

Figure 28. Short-Circuit Current vs Temperature

INA1650-Q1 INA1651-Q1 new_C907_SBOS772.png

Figure 30. Negative Output Voltage vs Output Current

INA1650-Q1 INA1651-Q1 new_C004_SBOS772.png

Figure 32. Quiescent Current vs Temperature

INA1650-Q1 INA1651-Q1 ai_C007_SBOS818.png

REF A/B connected to 0 V

Figure 34. Input Common-Mode Voltage vs Output Voltage

INA1650-Q1 INA1651-Q1 ai_C009_SBOS818.png

REF A/B connected to VMID(OUT)

Figure 36. Input Common-Mode Voltage vs Output Voltage

INA1650-Q1 INA1651-Q1 ai_C011_SBOS818.png

REF A/B connected to 0 V

Figure 38. Input Common-Mode Voltage vs Output Voltage

7 Detailed Description

7.1 Overview

The INA165x-Q1 family combines high-performance audio operational amplifier cores with high-precision resistor networks to provide exceptional audio performance and rejection of noise that may be externally coupled into the audio signal path. The two line-receiver channels of the INA1650-Q1, and the single line receiver channel of the INA1651-Q1, use an instrumentation amplifier topology with a fixed unity gain to provide high input impedance and a high common-mode rejection ratio (CMRR). Unlike other line receiver products that use a simple four-resistor difference amplifier topology, the INA165x-Q1 topology provides excellent CMRR even with mismatched source impedances.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Audio Signal Path

Figure 39 highlights the basic elements present in the audio signal pathway of the INA165x-Q1 line receivers. The primary elements are input biasing resistors, electromagnetic interference (EMI) filtering, input buffers, and a difference amplifier. The primary role of an audio line receiver is to convert a differential input signal into a single-ended output signal while rejecting noise that is common to both inputs (common-mode noise). The difference amplifier (which consists of an op amp and four matched 10-kΩ resistors) accomplishes this task. The basic transfer function of the circuit is shown in Equation 1:

Equation 1. INA1650-Q1 INA1651-Q1 FBD_eq_001.gif

Figure 39. INA165x-Q1 Audio Signal Path (Single Channel Shown)

The input buffers prevent external resistances (such as those from the PCB, connectors, or cables) from ruining the precise matching of the internal 10-kΩ resistors that degrade the high common-mode rejection of the difference amplifier. As is typical of many amplifiers, a small bias current flows into or out of the buffer amplifier inputs. This current must flow to a common potential for the buffer to function properly. The input biasing resistors provide an internal pathway for this current to the COM pin. The COM pin connects to ground in a dual-supply system, or to the output of the internal supply divider, VMID(OUT), in single-supply applications. Finally, EMI filtering is added to the input buffers to prevent high-frequency interference signals from propagating through the audio signal pathway.

7.3.2 Supply Divider

The INA165x-Q1 have an integrated supply-divider circuit that biases the input common-mode voltage and output reference voltage to the halfway point between the applied power supply voltages. The nominal output voltage of the supply divider circuit is shown in Equation 2:

Equation 2. INA1650-Q1 INA1651-Q1 FBD_eq_002.gif

Figure 40 illustrates the internal topology of the supply-divider circuit. The supply divider consists of two 500-kΩ resistors connected between the VCC and VEE pins of the INA165x-Q1. The noninverting input of a buffer amplifier is connected to the midpoint of the voltage divider that is formed by the 500-kΩ resistors. The buffer amplifier provides a low-impedance output that is required to bias the REF pins without degrading the CMRR. For dual-supply applications where the supply divider circuit is not used, no connection is required for the VMID(IN) or VMID(OUT) pins.

Figure 40. Internal Supply Divider Circuit