ZHCSG16A January   2017  – May 2017 LMK61E0M

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  3.3-V LVCMOS Output Characteristics
    7. 6.7  OE Input Characteristics
    8. 6.8  ADD Input Characteristics
    9. 6.9  Frequency Tolerance Characteristics
    10. 6.10 Frequency Margining Characteristics
    11. 6.11 Power-On/Reset Characteristics (VDD)
    12. 6.12 I2C-Compatible Interface Characteristics (SDA, SCL)
    13. 6.13 Other Characteristics
    14. 6.14 PLL Clock Output Jitter Characteristics
    15. 6.15 Additional Reliability and Qualification
    16. 6.16 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Block-Level Description
      2. 8.3.2  Device Configuration Control
      3. 8.3.3  Register File Reference Convention
      4. 8.3.4  Configuring the PLL
      5. 8.3.5  Integrated Oscillator
      6. 8.3.6  Reference Divider and Doubler
      7. 8.3.7  Phase Frequency Detector
      8. 8.3.8  Feedback Divider (N)
      9. 8.3.9  Fractional Engine
      10. 8.3.10 Charge Pump
      11. 8.3.11 Loop Filter
      12. 8.3.12 VCO Calibration
      13. 8.3.13 High-Speed Output Divider
      14. 8.3.14 High-Speed Clock Output
      15. 8.3.15 Device Status
        1. 8.3.15.1 Loss of Lock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Interface and Control
      2. 8.4.2 DCXO Mode and Frequency Margining
        1. 8.4.2.1 DCXO Mode
        2. 8.4.2.2 Fine Frequency Margining
        3. 8.4.2.3 Coarse Frequency Margining
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Block Register Write
      3. 8.5.3 Block Register Read
      4. 8.5.4 Write SRAM
      5. 8.5.5 Write EEPROM
      6. 8.5.6 Read SRAM
      7. 8.5.7 Read EEPROM
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  VNDRID_BY1 Register; R0
        2. 8.6.1.2  VNDRID_BY0 Register; R1
        3. 8.6.1.3  PRODID Register; R2
        4. 8.6.1.4  REVID Register; R3
        5. 8.6.1.5  SLAVEADR Register; R8
        6. 8.6.1.6  EEREV Register; R9
        7. 8.6.1.7  DEV_CTL Register; R10
        8. 8.6.1.8  XO_CAPCTRL_BY1 Register; R16
        9. 8.6.1.9  XO_CAPCTRL_BY0 Register; R17
        10. 8.6.1.10 CMOSCTL Register; R20
        11. 8.6.1.11 DIFFCTL Register; R21
        12. 8.6.1.12 OUTDIV_BY1 Register; R22
        13. 8.6.1.13 OUTDIV_BY0 Register; R23
        14. 8.6.1.14 RDIVCMOSCTL Register; R24
        15. 8.6.1.15 PLL_NDIV_BY1 Register; R25
        16. 8.6.1.16 PLL_NDIV_BY0 Register; R26
        17. 8.6.1.17 PLL_FRACNUM_BY2 Register; R27
        18. 8.6.1.18 PLL_FRACNUM_BY1 Register; R28
        19. 8.6.1.19 PLL_FRACNUM_BY0 Register; R29
        20. 8.6.1.20 PLL_FRACDEN_BY2 Register; R30
        21. 8.6.1.21 PLL_FRACDEN_BY1 Register; R31
        22. 8.6.1.22 PLL_FRACDEN_BY0 Register; R32
        23. 8.6.1.23 PLL_MASHCTRL Register; R33
        24. 8.6.1.24 PLL_CTRL0 Register; R34
        25. 8.6.1.25 PLL_CTRL1 Register; R35
        26. 8.6.1.26 PLL_LF_R2 Register; R36
        27. 8.6.1.27 PLL_LF_C1 Register; R37
        28. 8.6.1.28 PLL_LF_R3 Register; R38
        29. 8.6.1.29 PLL_LF_C3 Register; R39
        30. 8.6.1.30 PLL_CALCTRL Register; R42
        31. 8.6.1.31 NVMSCRC Register; R47
        32. 8.6.1.32 NVMCNT Register; R48
        33. 8.6.1.33 NVMCTL Register; R49
        34. 8.6.1.34 MEMADR Register; R51
        35. 8.6.1.35 NVMDAT Register; R52
        36. 8.6.1.36 RAMDAT Register; R53
        37. 8.6.1.37 NVMUNLK Register; R56
        38. 8.6.1.38 INT_LIVE Register; R66
        39. 8.6.1.39 SWRST Register; R72
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 PLL Loop Filter Design
        2. 9.2.2.2 Spur Mitigation Techniques
          1. 9.2.2.2.1 Phase Detection Spur
          2. 9.2.2.2.2 Integer Boundary Fractional Spur
          3. 9.2.2.2.3 Primary Fractional Spur
          4. 9.2.2.2.4 Sub-Fractional Spur
        3. 9.2.2.3 Device Programming
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ensured Thermal Reliability
      2. 11.1.2 Best Practices for Signal Integrity
      3. 11.1.3 Recommended Solder Reflow Profile
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

Detailed Description

Overview

The LMK61E0 is a programmable oscillator family that generates commonly used reference clocks. LMK61E0M supports 3.3-V LVCMOS outputs with less than 1000-fs RMS max jitter in integer PLL and fractional PLL modes.

Functional Block Diagram

LMK61E0M new_block_diagram_snas674.gif

NOTE

Control blocks are compatible with 1.8-V, 2.5-V, and 3.3-V I/O voltage levels.

Feature Description

Device Block-Level Description

The LMK61E0 is an integrated oscillator that includes a 50-MHz crystal and a fractional PLL with integrated VCO that supports a frequency range of 4.6 GHz to 5.6 GHz. The PLL block consists of a phase frequency detector (PFD), charge pump, integrated passive loop filter, a feedback divider that can support both integer and fractional values and a delta-sigma engine for noise suppression in fractional PLL mode. Completing the device is the combination of an integer output divider and an LVCMOS output buffer. The PLL is powered by on-chip low dropout (LDO) linear voltage regulators and the regulated supply network is partitioned such that the sensitive analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs provide isolation to the PLL from any noise in the external power supply rail. The device supports fine and coarse frequency margining by changing the settings of the integrated oscillator and the output divider respectively.

Device Configuration Control

The LMK61E0 supports I2C programming interface where an I2C host can update any device configuration after the device enables the host interface and the host writes a sequence that updates the device registers. Once the device configuration is set, the host can also write to the on-chip EEPROM for a new set of power-up defaults based on the configuration pin settings in the soft pin configuration mode.

Register File Reference Convention

Figure 4 shows the method that this document employs to refer to an individual register bit or a grouping of register bits. If a drawing or text references an individual bit the format is to specify the register number first and the bit number second. The LMK61E0 contains 38 registers that are 8 bits wide. The register addresses and the bit positions both begin with the number zero (0). The bit address is placed in brackets or after a period. The first bit in the register file is address R0[0] or R0.0 meaning that it is located in Register 0 and is bit position 0. The last bit in the register file is address R72[7] or R72.7 referring to the 8th bit of register address 72 (the 73rd register in the device). Figure 4 also lists specific bit positions as a number contained within a box. A box with the register address encloses the group of boxes that represent the bits relevant to the specific device circuitry in context.

LMK61E0M lmk61e2_register_reference_format_snas674.gif Figure 4. LMK61E0 Register Reference Format

Configuring the PLL

The PLL in LMK61E0 can be configured to accommodate various output frequencies either through I2C programming interface or, in the absence of programming the PLL defaults stored in EEPROM are loaded on power up. The PLL can be configured by setting the Reference Doubler, Integrated PLL Loop Filter, Feedback Divider, and Output Divider. The corresponding register addresses and configurations are detailed in the description section of each block below.

For the PLL to operate in closed-loop mode, the following condition in Equation 1 has to be met.

Equation 1. FVCO = FREF × (D/R) × [(INT + NUM/DEN)]

where

  • FVCO: PLL/VCO Frequency (4.6 GHz to 5.6 GHz)
  • FREF: 50-MHz reference input
  • D: Reference input doubler, 1=Disabled, 2=Enabled
  • R: Reference input divider, 1=Divider bypass, 4=Divide-by-4
  • INT: PLL feedback divider integer value (12 bits, 1 to 4095)
  • NUM: PLL feedback divider fractional numerator value (22 bits, 0 to 4194303)
  • DEN: PLL feedback divider fractional denominator value (22 bits, 1 to 4194303)

On LMK61E0M, the output frequency is related to the VCO frequency as given in Equation 2.

Equation 2. FOUT = FVCO / (P × OUTDIV)

where

  • P: VCO post-divider value, selectable between 4 or 5
  • OUTDIV: Output divider value (9 bits, 6 to 256)

The output frequency step size for every bit change in the numerator of the PLL fractional feedback divider is given in Equation 3.

Equation 3. STEPSIZE = (FREF × D)/ (R × P × OUTDIV × DEN)

Integrated Oscillator

The integrated oscillator in LMK61E0 features programmable load capacitances that can be set for the device to either operate at exactly its nominal oscillation frequency or operate at a fixed frequency offset from its nominal oscillation frequency. This is done by programming R16 and R17. More details on frequency margining are provided in Fine Frequency Margining.

Reference Divider and Doubler

The reference path has a divider and frequency doubler. The reference divider can be bypassed by programming R24[0] = 0 or can be set to divide-by-4 by programming R24[0] = 1. Enabling the divider results in a lower comparison frequency for the PLL and would result in a 6-dB increase in the in-band phase noise at the output of the LMK61E0 but would result in a finer frequency resolution at the output for every bit change in the numerator of fractional feedback divider. The reference doubler can be enabled by programming R34[5] = 1. Bypassing the divider allows for a higher comparison rate and improved in-band phase noise at the output of the LMK61E0. Enabling the doubler allows a higher comparison frequency for the PLL and would result in a 3-dB reduction in the in-band phase noise at the output of the LMK61E0. Enabling the doubler also results in higher reference and phase detector spurs which will be minimized by enabling the higher order components (R3, C3) of the loop filter and programming them to appropriate values. Disabling the doubler would result in a finer frequency resolution at the output for every bit change in the numerator of the fractional feedback divider and higher in-band phase noise on the device output than when the doubler is enabled. However, the reference and phase detector spurs would be lower on the device output than when the doubler is enabled.

Phase Frequency Detector

The Phase Frequency Detector (PFD) of the PLL takes inputs from the reference path and the feedback divider output and produces an output that is dependent on the phase and frequency difference between the two inputs. The input frequency of the PFD is equal to the 50-MHz reference frequency doubled if the reference doubler is enabled and then divided by 4 if the reference divider is enabled. The feedback frequency to the PFD must equal the reference path frequency to the PFD for the PLL to lock.

Feedback Divider (N)

The N divider of the PLL includes fractional compensation and can achieve any fractional denominator (DEN) from 1 to 4,194,303. The integer portion, INT (valid range 1-4095), is the whole part of the N divider value and the fractional portion, NUM / DEN, is the remaining fraction. INT, NUM, and DEN are programmed in R25/R26, R27/R28/R29, and R30/R31/R32, respectively. The total programmed N divider value, N, is determined by: N = INT + NUM / DEN. The output of the N divider sets the PFD frequency to the PLL. The feedback frequency to the PFD must equal the reference path frequency to the PFD for the PLL to lock. In DCXO mode, the NUM registers can be reprogrammed MSB first and LSB last to update the output frequency without glitches or spikes.

Fractional Engine

The delta signal modulator is a key component of the fractional engine and is involved in noise shaping for better phase noise and spurs in the band of interest. The order of the delta sigma modulator is selectable between integer mode and third order for fractional PLL mode, and it can be programmed in R33[1:0]. Dithering can be programmed in R33[3:2] and should be disabled for integer PLL mode and set to weak for fractional PLL mode.

Charge Pump

The PLL has charge pump slices of 1.6 mA, to be used when PLL is set to fractional mode, or 6.4 mA, to be used when PLL is set to integer mode. These slices can be selected by programming R34[3:0]. When PLL is set to fractional mode, a phase shift needs to be introduced to maintain a linear response and ensure consistent performance across operating conditions and a value of 0x2 should be programmed in R35[6:4]. When PLL is set to integer mode, a value of 0x0 should be programmed in R35[6:4].

Loop Filter

The LMK61E0 features a fully integrated loop filter for the PLL and supports programmable loop bandwidth from 100 kHz to 1 MHz. The loop filter components, R2, C1, R3, C3, can be configured by programming R36, R37, R38 and R39 respectively. The LMK61E0 features a fixed value of C2 of 10 nF. When PLL is configured in the fractional mode, R35[2] should be set to 1. When reference doubler is disabled for integer mode PLL, R35[2] should be set to 0 and R38[6:0] should be set to 0x00. When reference doubler is enabled for integer mode PLL, R35[2] should be set to 1 and R38 and R39 are written with the appropriate values. Figure 5 shows the loop filter structure of the PLL. It is important to set the PLL to best possible bandwidth to minimize output jitter.

LMK61E0M loop_filter_structure_pll_snas674.gif Figure 5. Loop Filter Structure of PLL

VCO Calibration

The PLL in LMK61E0 is made of LC VCO that is designed using high-Q monolithic inductors to oscillate between 4.6 GHz and 5.6 GHz and has low phase noise characteristics. The VCO must be calibrated to ensure that the clock outputs deliver optimal phase noise performance. Fundamentally, a VCO calibration establishes an optimal operating point within the tuning range of the VCO. Setting R72[1] to 1 causes a VCO recalibration and is necessary after device reconfiguration. VCO calibration automatically occurs on device power up.

High-Speed Output Divider

LMK61E0M has two integer dividers in series in the output signal path. The VCO post-divider divides the VCO frequency by 4 or 5 and is programmed in R22[5]. The following high-speed output divider supports divide values of 6 to 256 and is programmed in R22 and R23. The output divider also supports coarse frequency margining that can initiate as low as a 5% change in the output frequency. To change the output divider, R23 needs to be programmed first and then R22. This is necessary for the CMOS divider to load the correct divide value.

High-Speed Clock Output

The clock outputs on LMK61E0M support 3.3-V LVCMOS levels. Both pins can be individually set to be the same polarity or opposite polarity of the other, or can be set to high impedance or tri-state. By default, OUT0 is enabled and OUT1 is tristate. OUT0 is controlled by R20[2] and OUT1 is controlled by R24[4]. The slew rate of the LVCMOS output can be set to fast or slow by programming R22[7:6] = 0x0 or 0x2.

Device Status

The PLL loss of lock and PLL calibration status can be monitored by reading R66[1:0]. These bits represent a logic-high interrupt output and are self-cleared once the readback is complete.

Loss of Lock

The PLL loss of lock detection circuit is a digital circuit that detects any frequency error, even a single cycle slip. Loss of lock may occur when an incorrect PLL configuration is programmed or the VCO has not been recalibrated.

Device Functional Modes

Interface and Control

The host (DSP, Microcontroller, FPGA, etc) configures and monitors the LMK61E0 through the I2C port. The host reads and writes to a collection of control and status bits called the register map. The device blocks can be controlled and monitored through a specific grouping of bits located within the register file. The host controls and monitors certain device Wide critical parameters directly through register control and status bits. In the absence of the host, the LMK61E0 can be configured to operate from its on-chip EEPROM. The EEPROM array is automatically copied to the device registers upon power up. The user has the flexibility to rewrite the contents of EEPROM from the SRAM up to 100 times.

Within the device registers, there are certain bits that have read or write access. Other bits are read-only (an attempt to write to a read-only bit will not change the state of the bit). Certain device registers and bits are reserved meaning that they must not be changed from their default reset state. Figure 6 shows interface and control blocks within LMK61E0 and the arrows refer to read access from and write access to the different embedded memories (EEPROM, SRAM).

LMK61E0M lmk61e2_interface_and_control_block_snas674.gif Figure 6. LMK61E0 Interface and Control Block

DCXO Mode and Frequency Margining

DCXO Mode

In applications that require the LMK61E0 as part of a PLL that is implemented in another device like an FPGA, it can be used as a digitally controlled oscillator (DCXO) where the frequency control word can be passed along through I2C to the LMK61E0 on a regular basis which in turn updates the numerator of its fractional feedback divider by the required amount. In such a scenario, the entire portion of numerator for the fractional feedback divider must be written on every attempt MSB first and LSB last to ensure that the output frequency does not jump during the update, as described in Feedback Divider (N). In every update cycle, a total of 46 bits needs to be updated leading to a maximum update rate of 8.7 kHz with a maximum I2C rate of 1 Mbps. The minimum step size of 0.55 ppb (parts per billion) is achieved for the maximum VCO frequency of 5.6 GHz and when reference input doubler is disabled and reference divider is set to 4. The minimum step size of 4.96 ppb (parts per billion) is achieved for the maximum VCO frequency of 4.8 GHz and when reference input doubler is enabled and reference divider is bypassed.

Fine Frequency Margining

IEEE802.3 dictates that Ethernet frames stay compliant to the standard specifications when clocked with a reference clock that is within ±100 ppm of its nominal frequency. In the worst case, an RX node with its local reference clock at –100 ppm from its nominal frequency should be able to work seamlessly with a TX node that has its own local reference clock at +100 ppm from its nominal frequency. Without any clock compensation on the RX node, the read pointer will severely lag behind the write pointer and cause FIFO overflow errors. On the contrary, when the RX node’s local clock operates at +100 ppm from its nominal frequency and the TX node’s local clock operates at –100 ppm from its nominal frequency, FIFO underflow errors occur without any clock compensation.

To prevent such overflow and underflow errors from occurring, modern ASICs and FPGAs include a clock compensation scheme that introduces elastic buffers. Such a system, shown in Figure 7, is validated thoroughly during the validation phase by interfacing slower nodes with faster ones and ensuring compliance to IEEE802.3. The LMK61E0 provides the ability to fine tune the frequency of its outputs based on changing its load capacitance for the integrated oscillator. This fine tuning can be done through I2C as described in Integrated Oscillator. The change in load capacitance is implemented in a manner such that the output of LMK61E0 undergoes a smooth monotonic change in frequency.

Coarse Frequency Margining

Certain systems require the processors to be tested at clock frequencies that are slower or faster by 5% or 10%. The LMK61E0 offers the ability to change its output divider for the desired change from its nominal output frequency as explained in High-Speed Output Divider.

LMK61E0M system_implementation_clock_compensation_snas674.gif Figure 7. System Implementation With Clock Compensation for Standards Compliance

Programming

I2C Serial Interface

The I2C port on the LMK61E0 works as a slave device and supports both the 100-kHz standard mode and 1-MHz fast mode operations. Fast mode imposes a glitch tolerance requirement on the control signals. Therefore, the input receivers ignore pulses of less than 50-ns duration. The I2C timing is given in I2C-Compatible Interface Characteristics (SDA, SCL). The timing diagram is given in Figure 8.

LMK61E0M i2c_timing_diagram_snas674.gif Figure 8. I2C Timing Diagram

In an I2C bus system, the LMK61E0 acts as a slave device and is connected to the serial bus (data bus SDA and lock bus SCL). These are accessed via a 7-bit slave address transmitted as part of an I2C packet. Only the device with a matching slave address responds to subsequent I2C commands. In soft pin mode, the LMK61E0 allows up to three unique slave devices to occupy the I2C bus based on the pin strapping of ADD (tied to VDD, GND or left open). The device slave address is 10110xx (the two LSBs are determined by the ADD pin).

During the data transfer through the I2C interface, one clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can change only when the clock signal on the SCL line is low. The start data transfer condition is characterized by a high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is characterized by a low-to-high transition on the SDA line while SCL is high. The start and stop conditions are always initiated by the master. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit and bytes are sent MSB first. The I2C register structure of the LMK61E0 is shown in Figure 9.

LMK61E0M i2c_register_structure_snas674.gif Figure 9. I2C Register Structure

The acknowledge bit (A) or non-acknowledge bit (A’) is the 9th bit attached to any 8-bit data byte and is always generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A’ = 0). A = 0 is done by pulling the SDA line low during the 9th clock pulse and A’ = 0 is done by leaving the SDA line high during the 9th clock pulse.

The I2C master initiates the data transfer by asserting a start condition which initiates a response from all slave devices connected to the serial bus. Based on the 8-bit address byte sent by the master over the SDA line (consisting of the 7-bit slave address (MSB first) and an R/W’ bit), the device whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data transfer with the master.

After the data transfer has occurred, stop conditions are established. In write mode, the master asserts a stop condition to end data transfer during the 10th clock pulse following the acknowledge bit for the last data byte from the slave. In read mode, the master receives the last data byte from the slave but does not pull SDA low during the 9th clock pulse. This is known as a non-acknowledge bit. By receiving the non-acknowledge bit, the slave knows the data transfer is finished and enters the idle mode. The master then takes the data line low during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition. A generic transaction is shown in Figure 10.

LMK61E0M generic_programming_sequence_snas674.gif Figure 10. Generic Programming Sequence

The LMK61E0 I2C interface supports Block Register Write/Read, Read/Write SRAM, and Read/Write EEPROM operations. For Block Register Write/Read operations, the I2C master can individually access addressed registers that are made of an 8-bit data byte. The offset of the indexed register is encoded in the register address, as described in Table 1 below.

Table 1. Slave Address Byte

DEVICE A6 A5 A4 A3 A2 ADD pin R/W
LMK61E0 1 0 1 1 0 0x0, 0x1 or 0x3 1/0

Block Register Write

The I2C Block Register Write transaction is illustrated in Figure 11 and consists of the following sequence.

  1. Master issues a Start Condition.
  2. Master writes the 7-bit Slave Address following by a Write bit.
  3. Master writes the 8-bit Register address as the CommandCode of the programming sequence.
  4. Master writes one or more data bytes each of which should be acknowledged by the slave. The slave increments the internal register address after each byte.
  5. Master issues a Stop Condition to terminate the transaction.
LMK61E0M block_register_write_programming_sequence_snas674.gif Figure 11. Block Register Write Programming Sequence

Block Register Read

The I2C Block Register Read transaction is illustrated in Figure 12 and consists of the following sequence.

  1. Master issues a Start Condition.
  2. Master writes the 7-bit Slave Address followed by a Write bit.
  3. Master writes the 8-bit Register address as the CommandCode of the programming sequence.
  4. Master issues a Repeated Start Condition.
  5. Master writes the 7-bit Slave Address following by a Read bit.
  6. Slave returns one or more data bytes as long as the Master continues to acknowledge them. The slave increments the internal register address after each byte.
  7. Master issues a Stop Condition to terminate the transaction.
LMK61E0M block_register_read_programming_sequence_snas674.gif Figure 12. Block Register Read Programming Sequence

Write SRAM

The on-chip SRAM is a volatile, shadow memory array used to temporarily store register data, and is intended only for programming the non-volatile EEPROM. The SRAM has the identical data format as the EEPROM map. The register configuration data can be transferred to the SRAM array through special memory access registers in the register map. To successfully program the SRAM, the complete base array and at least one page should be written. The following details the programming sequence to transfer the device registers into the SRAM.

  1. Program the device registers to match a desired setting.
  2. Write a 1 to R49[6]. This ensures that the device registers are copied to the SRAM.

The SRAM can also be written with particular values according to the following programming sequence.

  1. Write the SRAM address in R51.
  2. Write the desired data byte in R53 in the same I2C transaction and this data byte will be written to the address specified in the step above. Any additional access that is part of the same transaction will cause the SRAM address to be incremented and a write will take place to the next SRAM address. Access to SRAM will terminate at the end of current I2C transaction.

NOTE

It is possible to increment SRAM address incorrectly when 2 successive accesses are made to R51.

Write EEPROM

The on-chip EEPROM is a non-volatile memory array used to permanently store register data for a custom device start-up configuration setting to initialize registers upon power up or POR. The EEPROM is comprised of bits shown in the EEPROM Map. The transfer must first happen to the SRAM and then to the EEPROM. During “EEPROM write”, R49[2] is a 1 and the EEPROM contents cannot be accessed. The following details the programming sequence to transfer the entire contents of SRAM to EEPROM.

  1. Make sure the "Write SRAM" procedure (Write SRAM) was done to commit the register settings to the SRAM with start-up configurations intended for programming to the EEPROM.
  2. Write 0xBE to R56. This provides basic protection from inadvertent programming of EEPROM.
  3. Write a 1 to R49[0]. This programs the entire SRAM contents to EEPROM. Once completed, the contents in R48 will increment by 1. R48 contains the total number of EEPROM programming cycles that are successfully completed.
  4. Write 0x00 to R56 to protect against inadvertent programming of EEPROM.

Read SRAM

The contents of the SRAM can be read out, one word at a time, starting with that of the requested address. Following details the programming sequence for an SRAM read by address.

  1. Write the SRAM address in R51.
  2. The SRAM data located at the address specified in the step above can be obtained by reading R53 in the same I2C transaction. Any additional access that is part of the same transaction will cause the SRAM address to be incremented and a read will take place of the next SRAM address. Access to SRAM will terminate at the end of current I2C transaction.

NOTE

It is possible to increment SRAM address incorrectly when 2 successive accesses are made to R51.

Read EEPROM

The contents of the EEPROM can be read out, one word at a time, starting with that of the requested address. Following details the programming sequence for an EEPROM read by address.

  1. Write the EEPROM address in R51.
  2. The EEPROM data located at the address specified in the step above can be obtained by reading R52 in the same I2C transaction. Any additional access that is part of the same transaction will cause the EEPROM address to be incremented and a read will take place of the next EEPROM address. Access to EEPROM will terminate at the end of current I2C transaction.

NOTE

It is possible to increment EEPROM address incorrectly when 2 successive accesses are made to R51.

Register Maps

Any bit that is labeled as RESERVED should be written with a 0.

Table 2. EEPROM Map

BYTE NO. BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
2 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
3 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
4 NVMSCRC[7] NVMSCRC[6] NVMSCRC[5] NVMSCRC[4] NVMSCRC[3] NVMSCRC[2] NVMSCRC[1] NVMSCRC[0]
5 NVMCNT[7] NVMCNT[6] NVMCNT[5] NVMCNT[4] NVMCNT[3] NVMCNT[2] NVMCNT[1] NVMCNT[0]
6 1 RESERVED RESERVED RESERVED RESERVED 1 RESERVED RESERVED
7 RESERVED RESERVED 1 RESERVED RESERVED RESERVED RESERVED 1
8 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
9 SLAVEADR[7] SLAVEADR[6] SLAVEADR[5] SLAVEADR[4] SLAVEADR[3] RESERVED RESERVED RESERVED
10 EEREV[7] EEREV[6] EEREV[5] EEREV[4] EEREV[3] EEREV[2] EEREV[1] EEREV[0]
11 RESERVED PLL_PDN RESERVED RESERVED RESERVED RESERVED AUTOSTRT RESERVED
14 RESERVED RESERVED RESERVED RESERVED RESERVED 1 RESERVED 1
15 RESERVED XO_CAPCTRL[1] XO_CAPCTRL[0] XO_CAPCTRL[9] XO_CAPCTRL[8] XO_CAPCTRL[7] XO_CAPCTRL[6] XO_CAPCTRL[5]
16 XO_CAPCTRL[4] XO_CAPCTRL[3] XO_CAPCTRL[2] RESERVED RESERVED RESERVED RESERVED RESERVED
19 RESERVED RESERVED OUT0_HIZ CMOS_MUTE RESERVED OUT1_INV OUT0_INV RESERVED
20 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
21 RESERVED RESERVED RESERVED OUT1_HIZ RESERVED RESERVED RESERVED PLL_RDIV
22 PLL_NDIV[11] PLL_NDIV[10] PLL_NDIV[9] PLL_NDIV[8] PLL_NDIV[7] PLL_NDIV[6] PLL_NDIV[5] PLL_NDIV[4]
23 PLL_NDIV[3] PLL_NDIV[2] PLL_NDIV[1] PLL_NDIV[0] PLL_NUM[21] PLL_NUM[20] PLL_NUM[19] PLL_NUM[18]
24 PLL_NUM[17] PLL_NUM[16] PLL_NUM[15] PLL_NUM[14] PLL_NUM[13] PLL_NUM[12] PLL_NUM[11] PLL_NUM[10]
25 PLL_NUM[9] PLL_NUM[8] PLL_NUM[7] PLL_NUM[6] PLL_NUM[5] PLL_NUM[4] PLL_NUM[3] PLL_NUM[2]
26 PLL_NUM[1] PLL_NUM[0] PLL_DEN[21] PLL_DEN[20] PLL_DEN[19] PLL_DEN[18] PLL_DEN[17] PLL_DEN[16]
27 PLL_DEN[15] PLL_DEN[14] PLL_DEN[13] PLL_DEN[12] PLL_DEN[11] PLL_DEN[10] PLL_DEN[9] PLL_DEN[8]
28 PLL_DEN[7] PLL_DEN[6] PLL_DEN[5] PLL_DEN[4] PLL_DEN[3] PLL_DEN[2] PLL_DEN[1] PLL_DEN[0]
29 PLL_
DTHRMODE[1]
PLL_DTHRMODE[0] PLL_ORDER[1] PLL_ORDER[0] RESERVED RESERVED PLL_D PLL_CP[3]
30 PLL_CP[2] PLL_CP[1] PLL_CP[0] PLL_CP_PHASE_
SHIFT[2]
PLL_CP_PHASE_
SHIFT[1]
PLL_CP_PHASE_
SHIFT[0]
PLL_ENABLE_
C3[2]
PLL_ENABLE_
C3[1]
31 PLL_ENABLE_
C3[0]
PLL_LF_R2[7] PLL_LF_R2[6] PLL_LF_R2[5] PLL_LF_R2[4] PLL_LF_R2[3] PLL_LF_R2[2] PLL_LF_R2[1]
32 PLL_LF_R2[0] PLL_LF_C1[2] PLL_LF_C1[1] PLL_LF_C1[0] PLL_LF_R3[6] PLL_LF_R3[5] PLL_LF_R3[4] PLL_LF_R3[3]
33 PLL_LF_R3[2] PLL_LF_R3[1] PLL_LF_R3[0] PLL_LF_C3[2] PLL_LF_C3[1] PLL_LF_C3[0] CMOS_SLEWRATE[1] CMOS_SLEWRATE[0]
34 PRE_DIV OUT_DIV[8] OUT_DIV[7] OUT_DIV[6] OUT_DIV[5] OUT_DIV[4] OUT_DIV[3] OUT_DIV[2]
35 OUT_DIV[1] OUT_DIV[0] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

The default/reset values for each register is specified for LMK61E0.

Table 3. Register Map

NAME ADDR RESET BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
VNDRID_BY1 0 0x10 VNDRID[15:8]
VNDRID_BY0 1 0x0B VNDRID[7:0]
PRODID 2 0x33 PRODID[7:0]
REVID 3 0x00 REVID[7:0]
SLAVEADR 8 0xB0 SLAVEADR[7:1] RESERVED
EEREV 9 0x00 EEREV[7:0]
DEV_CTL 10 0x01 RESERVED PLL_PDN RESERVED ENCAL AUTOSTRT
XO_CAPCTRL_
BY1
16 0x00 RESERVED XO_CAPCTRL[1:0]
XO_CAPCTRL_
BY0
17 0x00 XO_CAPCTRL[9:2]
CMOSCTL 20 0x00 RESERVED OUT0_HIZ CMOS_MUTE RESERVED
DIFFCTL 21 0x01 RESERVED OUT1_INV OUT0_INV RESERVED
OUTDIV_BY1 22 0x00 CMOS_SLEWRATE[1:0] PRE_DIV RESERVED OUT_DIV[8]
OUTDIV_BY0 23 0x20 OUT_DIV[7:0]
RDIVCMOSCTL 24 0x00 RESERVED OUT1_HIZ RESERVED PLL_RDIV
PLL_NDIV_BY1 25 0x00 RESERVED PLL_NDIV[11:8]
PLL_NDIV_BY0 26 0x64 PLL_NDIV[7:0]
PLL_FRACNUM_
BY2
27 0x00 RESERVED PLL_NUM[21:16]
PLL_FRACNUM_
BY1
28 0x00 PLL_NUM[15:8]
PLL_FRACNUM_
BY0
29 0x00 PLL_NUM[7:0]
PLL_FRACDEN_
BY2
30 0x00 RESERVED PLL_DEN[21:16]
PLL_FRACDEN_
BY1
31 0x00 PLL_DEN[15:8]
PLL_FRACDEN_
BY0
32 0x00 PLL_DEN[7:0]
PLL_MASHCTRL 33 0x0C RESERVED PLL_DTHRMODE[1:0] PLL_ORDER[1:0]
PLL_CTRL0 34 0x24 RESERVED PLL_D RESERVED PLL_CP[3:0]
PLL_CTRL1 35 0x03 RESERVED PLL_CP_PHASE_SHIFT[2:0] RESERVED PLL_ENABLE_C3[2:0]
PLL_LF_R2 36 0x28 PLL_LF_R2[7:0]
PLL_LF_C1 37 0x00 RESERVED PLL_LF_C1[2:0]
PLL_LF_R3 38 0x00 RESERVED PLL_LF_R3[6:0]
PLL_LF_C3 39 0x00 RESERVED PLL_LF_C3[2:0]
PLL_CALCTRL 42 0x00 RESERVED PLL_CLSDWAIT[1:0] PLL_VCOWAIT[1:0]
NVMSCRC 47 0x00 NVMSCRC[7:0]
NVMCNT 48 0x00 NVMCNT[7:0]
NVMCTL 49 0x10 RESERVED REGCOMMIT NVMCRCERR NVMAUTOCRC NVMCOMMIT NVMBUSY NVMERASE NVMPROG
NVMLCRC 50 0x00 NVMLCRC[7:0]
MEMADR 51 0x00 RESERVED MEMADR[6:0]
NVMDAT 52 0x00 NVMDAT[7:0]
RAMDAT 53 0x00 RAMDAT[7:0]
NVMUNLK 56 0x00 NVMUNLK[7:0]
INT_LIVE 66 0x00 RESERVED LOL CAL
SWRST 72 0x00 RESERVED SWR2PLL RESERVED

Register Descriptions

VNDRID_BY1 Register; R0

VNDRID_BY1 and VNDRID_BY0 registers are used to store the unique 16-bit Vendor Identification number assigned to I2C vendors.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] VNDRID[15:8] R 0x10 N Vendor Identification Number Byte 1.

VNDRID_BY0 Register; R1

VNDRID_BY1 and VNDRID_BY0 registers are used to store the unique 16-bit Vendor Identification number assigned to I2C vendors.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] VNDRID[7:0] R 0x0B N Vendor Identification Number Byte 0.

PRODID Register; R2

The Product Identification Number is a unique 8-bit identification number used to identify the LMK61E0.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] PRODID[7:0] R 0x33 N Product Identification Number.

REVID Register; R3

The REVID register is used to identify the LMK61E0 mask revision.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] REVID[7:0] R 0x00 N Device Revision Number. The Device Revision Number is used to identify the LMK61E0 mask-set revision used to fabricate this device.

SLAVEADR Register; R8

The SLAVEADR register reflects the 7-bit I2C Slave Address value initialized from from on-chip EEPROM.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:1] SLAVEADR[7:1] R 0x58 Y I2C Slave Address. This field holds the 7-bit Slave Address used to identify this device during I2C transactions. The two least significant bits of the address can be configured using ADD pin as shown.
SLAVEADR[2:1] ADD pin
0 (0x0) 0
1 (0x1) Float
3 (0x3) 1
[0] RESERVED - - N Reserved.

EEREV Register; R9

The EEREV register provides an EEPROM image revision record. EEPROM Image Revision is automatically retrieved from EEPROM and stored in the EEREV register after a reset or after a EEPROM commit operation.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] EEREV[7:0] R 0x00 Y EEPROM Image Revision ID

DEV_CTL Register; R10

The DEV_CTL register holds the control functions described in the following table.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7] RESERVED - 0 Y Reserved.
[6] PLL_PDN RW 0 Y PLL Powerdown. The PLL_PDN bit determines whether PLL is automatically enabled and calibrated after a hardware reset. If the PLL_PDN bit is set to 1 during normal operation then PLL is disabled and the calibration circuit is reset. When PLL_PDN is then cleared to 0 PLL is re-enabled and the calibration sequence is automatically restarted.
PLL_PDN Value
0 PLL Enabled
1 PLL Disabled
[5] CMOS_SEL RW 1 Y Set to 1 for LMK61E0M.
[4:2] RESERVED[5:2] RW 0 Y Reserved.
[1] ENCAL RWSC 0 N Enable Frequency Calibration. Triggers PLL/VCO calibration on both PLLs in parallel on 0 –> 1 transition of ENCAL. This bit is self-clearing and set to a 0 after PLL/VCO calibration is complete. In powerup or software rest mode, AUTOSTRT takes precedence.
[0] AUTOSTRT RW 1 Y Autostart. If AUTOSTRT is set to 1 the device will automatically attempt to achieve lock and enable outputs after a device reset. A device reset can be triggered by the power-on-reset, RESETn pin or by writing to the RESETN_SW bit. If AUTOSTRT is 0 then the device will halt after the configuration phase, a subsequent write to set the AUTOSTRT bit to 1 will trigger the PLL Lock sequence.

XO_CAPCTRL_BY1 Register; R16

XO Margining Offset Value bits[9:8]

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:2] RESERVED[5:0] - - N Reserved.
[1:0] XO_CAPCTRL [1:0] RW 0x0 Y XO Offset Value bits [1:0]

XO_CAPCTRL_BY0 Register; R17

XO Margining Offset Value bits[7:0]

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] XO_CAPCTRL [9:2] RW 0x80 Y XO Offset Value bits[9:2]

CMOSCTL Register; R20

The CMOSCTL register provides control over Output for LMK61E0M.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:3] RESERVED - - N Reserved.
[2] OUT0_HIZ RW 0 Y Controls OUT0 in LMK61E0M. When set to 1, the output is tri-stated with high impedance. When set to 0, the output is in normal operation.
[1] CMOS_MUTE RW 0 Y Output channel mute in LMK61E0M.
[0] RESERVED - - N Reserved.

DIFFCTL Register; R21

LVCMOS channel inversion is controlled by the OUT0_INV and OUT1_INV registers.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:6] RESERVED - - N Reserved.
[5] OUT1_INV RW 0 Y Inversion for CMOS output channel 1.
[4] OUT0_INV RW 0 Y Inversion for CMOS output channel 0.
[3:0] RESERVED - - N Reserved.

OUTDIV_BY1 Register; R22

The 9-bit output integer divider value is set by the OUTDIV_BY1 and OUTDIV_BY0 registers.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:6] CMOS_SLEWRATE[1:0] RW 0x0 Y Sets LVCMOS output slew rate in LMK61E0M. 0x0 sets to fast mode and 0x2 sets to slow mode.
[5] PRE_DIV RW 0 Y Sets LVCMOS output pre-divider in LMK61E0M. 0 sets to divide-by-4 and 1 sets to divide-by-5.
[4:1] RESERVED RW 0x0 Y Reserved.
[0] OUT_DIV[8] RW 0 Y Channel's Output Divider Byte 1 (Bit 8). The Channel Divider, OUT_DIV, is a 9-bit divider. The valid register values range from 5-255, which correspond with divide ratios of 6-256. To change the output divider, R23 needs to be programmed first and then R22. This is necessary for the CMOS divider to load the correct divide value.
OUT_DIV DIVIDE RATIO
0-4 RESERVED
5 (0x006) 6
6 (0x007) 7
254 (0x0FF) 255
255 (0x100) 256

OUTDIV_BY0 Register; R23

The 9-bit output integer divider value is set by the OUTDIV_BY1 and OUTDIV_BY0 registers.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] OUT_DIV[7:0] RW 0x20 Y Channel's Output Divider Byte 0 (Bits 7-0). To change the output divider, R23 needs to be programmed first and then R22. This is necessary for the CMOS divider to load the correct divide value.

RDIVCMOSCTL Register; R24

Sets R divider and CMOS OUT1 control for LMK61E0M.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:5] RESERVED - - N Reserved.
[4] OUT1_HIZ RW 1 Y Controls OUT1 in LMK61E0M. When set to 1, the output is tri-stated with high impedance. When set to 0, the output is in normal operation.
[3:1] RESERVED - - N Reserved.
[0] PLL_RDIV RW 0 Y On LMK61E0M, R divider is set to divide-by-4 when set to 1 and R divider is bypassed when set to 0.

PLL_NDIV_BY1 Register; R25

The 12-bit N integer divider value for PLL is set by the PLL_NDIV_BY1 and PLL_NDIV_BY0 registers.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:4] RESERVED - - N Reserved.
[3:0] PLL_NDIV[11:8] RW 0x0 Y PLL N Divider Byte 1. PLL Integer N Divider bits [11:8].

PLL_NDIV_BY0 Register; R26

The PLL_NDIV_BY0 register is described in the following table.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] PLL_NDIV[7:0] RW 0x32 Y PLL N Divider Byte 0. PLL Integer N Divider bits [7:0].

PLL_FRACNUM_BY2 Register; R27

The 22-bit Fractional Divider Numerator value for PLL is set by registers PLL_FRACNUM_BY2, PLL_FRACNUM_BY1 and PLL_FRACNUM_BY0.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:6] RESERVED - - N Reserved.
[5:0] PLL_NUM[21:16] RW 0x00 Y PLL Fractional Divider Numerator Byte 2. Bits [21:16]

PLL_FRACNUM_BY1 Register; R28

The PLL_FRACNUM_BY1 register is described in the following table.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] PLL_NUM[15:8] RW 0x00 Y PLL Fractional Divider Numerator Byte 1. Bits [15:8].

PLL_FRACNUM_BY0 Register; R29

The PLL_FRACNUM_BY0 register is described in the following table.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] PLL_NUM[7:0] RW 0x00 Y PLL Fractional Divider Numerator Byte 0. Bits [7:0]. When using DCXO mode, the fractional numerator bits in R27, R28, and R29 should be written in that order (MSB first and LSB last) to avoid intermediate frequency jumps.

PLL_FRACDEN_BY2 Register; R30

The 22-bit Fractional Divider Denominator value for PLL is set by registers PLL_FRACDEN_BY2, PLL_FRACDEN_BY1 and PLL_FRACDEN_BY0.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:6] RESERVED - - N Reserved.
[5:0] PLL_DEN[21:16] RW 0x00 Y PLL Fractional Divider Denominator Byte 2. Bits [21:16].

PLL_FRACDEN_BY1 Register; R31

The PLL_FRACDEN_BY1 register is described in the following table.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] PLL_DEN[15:8] RW 0x00 Y PLL Fractional Divider Denominator Byte 1. Bits [15:8].

PLL_FRACDEN_BY0 Register; R32

The PLL_FRACDEN_BY0 register is described in the following table.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] PLL_DEN[7:0] RW 0x00 Y PLL Fractional Divider Denominator Byte 0. Bits [7:0].

PLL_MASHCTRL Register; R33

The PLL_MASHCTRL register provides control of the fractional divider for PLL.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:4] RESERVED - - N Reserved.
[3:2] PLL_DTHRMODE[1:0] RW 0x3 Y Mash Engine dither mode control.
DITHERMODE Dither Configuration
0 (0x0) Weak
1 (0x1) Reserved
2 (0x2) Reserved
3 (0x3) Dither Disabled
[1:0] PLL_ORDER[1:0] RW 0x0 Y Mash Engine Order.
ORDER Order Configuration
0 (0x0) Integer Mode Divider
1 (0x1) Reserved
2 (0x2) Reserved
3 (0x3) 3rd order

PLL_CTRL0 Register; R34

The PLL_CTRL1 register provides control of PLL. The PLL_CTRL1 register fields are described in the following table.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:6] RESERVED RW 0x0 Y Reserved.
[5] PLL_D RW 1 Y PLL R Divider Frequency Doubler Enable. If PLL_D is 1 the R Divider Frequency Doubler is enabled.
[4] RESERVED - - N Reserved.
[3:0] PLL_CP[3:0] RW 0x8 Y PLL Charge Pump Current. Other combinations of PLL_CP[3:0] not in table below are reserved and not supported.
PLL_CP[3:0] PLL Charge Pump Current
4 (0x4) 1.6 mA
8 (0x8) 6.4 mA

PLL_CTRL1 Register; R35

The PLL_CTRL3 register provides control of PLL. The PLL_CTRL3 register fields are described in the following table.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7] RESERVED - - N Reserved.
[6:4] PLL_CP_PHASE_SHIFT[2:0] RW 0x0 Y Program Charge Pump Phase Shift.
PLL_CP_PHASE_SHIFT[2:0] Phase Shift
0 (0x0) No delay
1 (0x1) 1.3 ns for 100 MHz fPD
2 (0x2) 1 ns for 100 MHz fPD
3 (0x3) 0.9 ns for 100 MHz fPD
4 (0x4) 1.3 ns for 50 MHz fPD
5 (0x5) 1 ns for 50 MHz fPD
6 (0x6) 0.9 ns for 50 MHz fPD
7 (0x7) 0.7 ns for 50 MHz fPD
[3] RESERVED - - N Reserved.
[2] PLL_ENABLE_C3 RW 0 Y Disable third order capacitor in the low pass filter.
PLL_ENABLE_C3 MODE
0 2nd order loop filter recommended setting
1 Enables C3, 3rd order loop filter enabled
[1:0] RESERVED - 0x3 Y Reserved.

PLL_LF_R2 Register; R36

The PLL_LF_R2 register controls the value of the PLL Loop Filter R2.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] PLL_LF_R2[7:0] RW 0x08 Y PLL Loop Filter R2. NOTE: Table below lists commonly used R2 values but more selections are available.
PLL_LF_R2[7:0] R2 (Ω)
1 (0x01) 200
4 (0x04) 500
8 (0x08) 700
32 (0x20) 1600
48 (0x30) 2400
64 (0x40) 3200

PLL_LF_C1 Register; R37

The PLL_LF_C1 register controls the value of the PLL Loop Filter C1.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:3] RESERVED - - N Reserved.
[2:0] PLL_LF_C1[2:0] RW 0x0 Y PLL Loop Filter C1. The value in pF is given by 5 + 50 * PLL_LF_C1 (in decimal).

PLL_LF_R3 Register; R38

The PLL_LF_R3 register controls the value of the PLL Loop Filter R3.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7] RESERVED - - N Reserved.
[6:0] PLL_LF_R3[6:0] RW 0x00 Y PLL Loop Filter R3. NOTE: Table below lists commonly used R3 values but more selections are available.
PLL_LF_R3[6:0] R3 (Ω)
0 (0x00) 18
3 (0x03) 205
8 (0x08) 854
9 (0x09) 1136
12 (0x0C) 1535
17 (0x11) 1936
20 (0x14) 2335

PLL_LF_C3 Register; R39

The PLL_LF_C3 register controls the value of the PLL Loop Filter C3.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:3] RESERVED - - N Reserved.
[2:0] PLL_LF_C3[2:0] RW 0x0 Y PLL Loop Filter C3. The value in pF is given by 5 * PLL_LF_C3 (in decimal).

PLL_CALCTRL Register; R42

The PLL_CALCTRL register is described in the following table.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:4] RESERVED - - N Reserved.
[3:2] PLL_CLSDWAIT[1:0] RW 0x2 Y Closed Loop Wait Period. The CLSDWAIT field sets the closed loop wait period. Recommended value is 0x2.
CLSDWAIT Anlog closed loop VCO stabilization time
0 (0x0) 150 µs
1 (0x1) 300 µs
2 (0x2) 500 µs
3 (0x3) 2000 µs
[1:0] PLL_VCOWAIT[1:0] RW 0x1 Y VCO Wait Period. Recommended value is 0x1.
VCOWAIT VCO stabilization time
0 (0x0) 20 µs
1 (0x1) 400 µs
2 (0x2) 4000 µs
3 (0x3) 10000 µs

NVMSCRC Register; R47

The NVMSCRC register holds the Stored CRC (Cyclic Redundancy Check) byte that has been retreived from on-chip EEPROM.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] NVMSCRC[7:0] R 0x00 Y EEPROM Stored CRC.

NVMCNT Register; R48

The NVMCNT register is intended to reflect the number of on-chip EEPROM Erase/Program cycles that have taken place in EEPROM. The count is automatically incremented by hardware and stored in EEPROM.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] NVMCNT[7:0] R 0x00 Y EEPROM Program Count. The NVMCNT increments automatically after every EEPROM Erase/Program Cycle. The NVMCNT value is retreived automatically after reset, after a EEPROM Commit operation or after a Erase/Program cycle. The NVMCNT register will increment until it reaches its maximum value of 255 after which no further increments will take place.

NVMCTL Register; R49

The NVMCTL register allows control of the on-chip EEPROM Memories.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7] RESERVED - - N Reserved.
[6] REGCOMMIT RWSC 0 N REG Commit to EEPROM SRAM Array. The REGCOMMIT bit is used to initiate a transfer from the on-chip registers back to the corresponding location in the EEPROM SRAM Array. The REGCOMMIT bit is automatically cleared to 0 when the transfer is complete.
[5] NVMCRCERR R 0 N EEPROM CRC Error Indication. The NVMCRCERR bit is set to 1 if a CRC Error has been detected when reading back from on-chip EEPROM during device configuration.
[4] NVMAUTOCRC RW 1 N EEPROM Automatic CRC. When NVMAUTOCRC is 1 then the EEPROM Stored CRC byte is automatically calculated whenever a EEPROM program takes place.
[3] NVMCOMMIT RWSC 0 N EEPROM Commit to Registers. The NVMCOMMIT bit is used to initiate a transfer of the on-chip EEPROM contents to internal registers. The transfer happens automatically after reset or when NVMCOMMIT is set to 1. The NVMCOMMIT bit is automatically cleared to 0. The I2C registers cannot be read while a EEPROM Commit operation is taking place.
[2] NVMBUSY R 0 N EEPROM Program Busy Indication. The NVMBUSY bit is 1 during an on-chip EEPROM Erase/Program cycle. While NVMBUSY is 1 the on-chip EEPROM cannot be accessed.
[1] NVMERASE RWSC 0 N EEPROM Erase Start. The NVMERASE bit is used to begin an on-chip EEPROM Erase cycle. The Erase cycle is only initiated if the immediately preceding I2C transaction was a write to the NVMUNLK register with the appropriate code. The NVMERASE bit is automatically cleared to 0. The EEPROM Erase operation takes around 115ms.
[0] NVMPROG RWSC 0 N EEPROM Program Start. The NVMPROG bit is used to begin an on-chip EEPROM Program cycle. The Program cycle is only initiated if the immediately preceding I2C transaction was a write to the NVMUNLK register with the appropriate code. The NVMPROG bit is automatically cleared to 0. If the NVMERASE and NVMPROG bits are set simultaneously then an ERASE/PROGRAM cycle will be executed The EEPROM Program operation takes around 115ms.

MEMADR Register; R51

The MEMADR register holds 7-bits of the starting address for on-chip SRAM or EEPROM access.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7] RESERVED - - N Reserved.
[6:0] MEMADR[6:0] RW 0x00 N Memory Address. The MEMADR value determines the starting address for on-chip SRAM read/write access or on-chip EEPROM access. The internal address to access SRAM or EEPROM is automatically incremented; however the MEMADR register does not reflect the internal address in this way. When the SRAM or EEPROM arrays are accessed using the I2C interface only bits [4:0] of MEMADR are used to form the byte Wise address.

NVMDAT Register; R52

The NVMDAT register returns the on-chip EEPROM contents from the starting address specified by the MEMADR register.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] NVMDAT[7:0] R 0x00 N EEPROM Read Data. The first time an I2C read transaction accesses the NVMDAT register address, either because it was explicitly targeted or because the address was auto-incremented, the read transaction will return the EEPROM data located at the address specified by the MEMADR register. Any additional read's which are part of the same transaction will cause the EEPROM address to be incremented and the next EEPROM data byte will be returned. The I2C address will no longer be auto-incremented, i.e the I2C address will be locked to the NVMDAT register after the first access. Access to the NVMDAT register will terminate at the end of the current I2C transaction.

RAMDAT Register; R53

The RAMDAT register provides read and write access to the SRAM that forms part of the on-chip EEPROM module.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] RAMDAT[7:0] RW 0x00 N RAM Read/Write Data. The first time an I2C read or write transaction accesses the RAMDAT register address, either because it was explicitly targeted or because the address was auto-incremented, a read transaction will return the RAM data located at the address specified by the MEMADR register and a write transaction will cause the current I2C data to be written to the address specified by the MEMADR register. Any additional accesses which are part of the same transaction will cause the RAM address to be incremented and a read or write access will take place to the next SRAM address. The I2C address will no longer be auto-incremented, i.e the I2C address will be locked to the RAMDAT register after the first access. Access to the RAMDAT register will terminate at the end of the current I2C transaction.

NVMUNLK Register; R56

The NVMUNLK register provides a rudimentary level of protection to prevent inadvertent programming of the on-chip EEPROM.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:0] NVMUNLK[7:0] RW 0x00 N EEPROM Prog Unlock. The NVMUNLK register must be written immediately prior to setting the NVMPROG bit of register NVMCTL, otherwise the Erase/Program cycle will not be triggered. NVMUNLK must be written with a value of 0xBE.

INT_LIVE Register; R66

The INT_LIVE register reflects the current status of the interrupt sources.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:2] RESERVED - - N Reserved.
[1] LOL R 0 N Loss of Lock PLL.
[0] CAL R 0 N Calibration Active PLL.

SWRST Register; R72

The SWRST1 register provides software reset control for specific on-chip modules. Each bit in this register is individually self cleared after a write operation. The SWRST1 register will always return 0x00 in a read transaction.

BIT NO. FIELD TYPE RESET EEPROM DESCRIPTION
[7:2] RESERVED - - N Reserved.
[1] SWR2PLL RWSC 0 N Software Reset PLL. Setting SWR2PLL to 1 resets the PLL calibrator and clock dividers. This bit is automatically cleared to 0.
[0] RESERVED - - N Reserved.