ZHCSFO3D November   2016  – August 2021 LM5170-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply (VCC, VCCA)
      2. 8.3.2  Undervoltage Lockout (UVLO) and Master Enable or Disable
      3. 8.3.3  High Voltage Input (VIN, VINX)
      4. 8.3.4  Current Sense Amplifier
      5. 8.3.5  Control Commands
        1. 8.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 8.3.5.2 Direction Command (DIR)
        3. 8.3.5.3 Channel Current Setting Commands (ISETA or ISETD)
      6. 8.3.6  Channel Current Monitor (IOUT1, IOUT2)
      7. 8.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Ramp Generator
      10. 8.3.10 Soft Start
        1. 8.3.10.1 Soft-Start Control by the SS Pin
        2. 8.3.10.2 Soft Start by MCU Through the ISET Pin
        3. 8.3.10.3 The SS Pin as the Restart Timer
      11. 8.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)
      12. 8.3.12 PWM Comparator
      13. 8.3.13 Oscillator (OSC)
      14. 8.3.14 Synchronization to an External Clock (SYNCIN, SYNCOUT)
      15. 8.3.15 Diode Emulation
      16. 8.3.16 Power MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)
        1. 8.3.16.1 Failure Detection Selection at the SYNCOUT Pin
        2. 8.3.16.2 Nominal Circuit Breaker Function
      17. 8.3.17 Overvoltage Protection (OVPA, OVPB)
        1. 8.3.17.1 HV-V- Port OVP (OVPA)
        2. 8.3.17.2 LV-Port OVP (OVPB)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Multiphase Configurations (SYNCOUT, OPT)
        1. 8.4.1.1 Multiphase in Star Configuration
        2. 8.4.1.2 Configuration of 2, 3, or 4 Phases in Master-Slave Daisy-Chain Configurations
        3. 8.4.1.3 Configuration of 6 or 8 Phases in Master-Slave Daisy-Chain Configurations
      2. 8.4.2 Multiphase Total Current Monitoring
    5. 8.5 Programming
      1. 8.5.1 Dynamic Dead Time Adjustment
      2. 8.5.2 Optional UVLO Programming
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Key Waveforms
        1. 9.1.1.1 Typical Power-Up Sequence
        2. 9.1.1.2 One to Eight Phase Programming
      2. 9.1.2 Inner Current Loop Small Signal Models
        1. 9.1.2.1 Small Signal Model
        2. 9.1.2.2 Inner Current Loop Compensation
      3. 9.1.3 Compensating for the Non-Ideal Current Sense Resistor
      4. 9.1.4 Outer Voltage Loop Control
    2. 9.2 Typical Application
      1. 9.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Determining the Duty Cycle
          2. 9.2.1.2.2  Oscillator Programming
          3. 9.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 9.2.1.2.4  Current Sense (RCS)
          5. 9.2.1.2.5  Current Setting Limits (ISETA or ISETD)
          6. 9.2.1.2.6  Peak Current Limit
          7. 9.2.1.2.7  Power MOSFETS
          8. 9.2.1.2.8  Bias Supply
          9. 9.2.1.2.9  Boot Strap
          10. 9.2.1.2.10 RAMP Generators
          11. 9.2.1.2.11 OVP
          12. 9.2.1.2.12 Dead Time
          13. 9.2.1.2.13 IOUT Monitors
          14. 9.2.1.2.14 UVLO Pin Usage
          15. 9.2.1.2.15 VIN Pin Configuration
          16. 9.2.1.2.16 Loop Compensation
          17. 9.2.1.2.17 Soft Start
          18. 9.2.1.2.18 ISET Pins
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

Electrical Characteristics

FOSC = 100 kHz; VVCC = 10 V; VVIN = VHV-Port = 48 V and VLV-Port = 12 V, unless otherwise stated.(1)
PARAMETERTEST CONDITIONSMIN(3)TYP(2)MAX(3)UNIT
VIN SUPPLY (VIN, VINX)
ISHUTDOWNVIN pin current in shutdown modeVUVLO = 0 V10µA
ISTANDBYVIN pin current, no switchingVVCC > 9 V, VUVLO > 2.5 V, VEN1 = VEN2 = 0 V1mA
VIN to VINX disconnect switchVUVLO < 1 V or VVCC < 7.5 V5
VIN to VINX disconnect switchVUVLO > 2.6 V, VVCC > 9 V100Ω
VCC AND VCCA BIAS SUPPLIES
VCCUVLOVCC undervoltage detectionVVCC falling7.688.3V
VCCHYSVCC UVLO hysteresisVVCC rising8.18.58.9V
IVCC_SDVCC sink current in shutdown modeVUVLO = 0 V20µA
IVCC_SBVCC sink current in standby: no switchingVUVLO > 2.6 V, VEN1 = VEN2 = 0 V10mA
MASTER ON/OFF CONTROL (UVLO)
VUVLO_THUVLO release thresholdUVLO voltage rising2.42.52.6V
IHYSUVLO hysteresis currentUVLO source current when VUVLO > 2.6 V212529µA
VSDUVLO shutdown threshold (IC shutdown)UVLO voltage falling11.251.5V
UVLO shutdown releaseUVLO voltage rising above VSD0.150.250.35V
tUVLOUVLO glitch filter timeUVLO voltage falling2.5µs
UVLO internal pulldown current1µA
CHANNEL ENABLE INPUTS EN1 AND EN2
VILEnable input low stateDisabled the driver outputs1V
VIHEnable input high stateEnable the driver outputs2V
Internal pulldown impedanceEN1, EN2 internal pulldown resistor100kΩ
EN glitch filter time (the rising and falling edges)2µs
DIRECTION COMMAND (DIR)
VDIRCommand for current flowing from LV-Port to HV-Port (boost mode 12 V to 48 V)Actively pulled low by external circuit1V
Command for current flowing from HV-Port to LV-Port (buck mode 48 V to 12 V)Actively pulled high by external circuit2V
Standby (invalid DIR command)DIR neither active high nor active low1.5V
DIR glitch filterBoth rising and falling edges10µs
ISET INPUT (ISETA, ISETD)
GISETARegulated DC current sense voltage to ISETA voltage|VCSA – VCSB| = 50 mV19.72020.3mV/V
ISETA internal pulldown resistor170kΩ
GISETDConversion ratio of ISETA voltage to ISETD duty cycleISETD frequency = 10 kHz, Duty = 100%30.6331.2531.88mV / %
VISETD _LOISETD PWM signal low-state voltage1V
VISETD _HIISETD PWM signal high-state voltage2V
ISETD internal pulldown resistor100kΩ
ISETD internal decoder filter resistor (tied to ISETA pin)100kΩ
OUTPUT CURRENT MONITOR (IOUT1, IOUT2)
GIOUT_BK1IOUT1 and IOUT2 versus channel current sense voltage, in buck mode|VCSA – VCSB| = 50 mV, VDIR > 2 V4.955.1μA/mV
GIOUT_BST1IOUT1 and IOUT2 versus channel current sense voltage, in boost mode|VCSA – VCSB| = 50 mV, VDIR < 1 V4.955.1μA/mV
GIOUT_BK2IOUT1 and IOUT2 versus channel current sense voltage, in buck mode|VCSA – VCSB| = 10 mV, VDIR > 2 V, TJ = 25°C4.915.185.43μA/mV
GIOUT_BST2IOUT1 and IOUT2 versus channel current sense voltage, in boost mode|VCSA – VCSB| = 10 mV, VDIR < 1 V, TJ = 25°C4.474.775.1μA/mV
IOUT1 and IOUT2 DC offset currents|VCSA – VCSB| = 0 mV222528µA
CURRENT SENSE AMPLIFIER (BOTH CHANNELS)
GCS_BK1Amplifier output to current sense voltage in buck mode|VCSA – VCSB| = 50 mV, VDIR > 2 V49.255050.75V/V
GCS_BST1Amplifier output to current sense voltage in boost mode|VCSA – VCSB| = 50 mV, VDIR < 1 V49.255050.75V/V
GCS_BK2Amplifier output to current sense voltage in buck mode|VCSA – VCSB| = 10 mV, VDIR > 2 V, TJ = 25°C495255V/V
GCS_BST2Amplifier output to current sense voltage in boost mode|VCSA – VCSB| = 10 mV, VDIR < 1 V, TJ = 25°C454851V/V
BWCSAmplifier bandwidth10MHz
TRANSCONDUCTION AMPLIFIER (COMP1, COMP2)
GmTransconductance1mA/V
ICOMPOutput source current limitVISETA = 2.5 V, |VCSA – VCSB| = 10 mV2mA
Output sink current limitVISETA = 0 V, |VCSA – VCSB| = 50 mV–2mA
BWgmAmplifier bandwidth4MHz
PWM COMPARATOR
COMP to output delay50ns
COMP to PWM offset1V
TOFF(min)Minimum OFF time150200250ns
RAMP GENERATOR (RAMP1 AND RAMP2)
RAMP discharge device RDS(on)15Ω
Threshold voltage for valid ramp signal0.6V
PEAK CURRENT LIMIT (IPK)
IPK internal current source24.3752525.625µA
IPKBuckCurrent sense voltage versus cycle-by-cycle limit threshold voltage given at IPK pin, in buck modeRIPK = 40 kΩ, VDIR > 2 V35.84658.9mV/V
IPKBoostCurrent sense voltage versus cycle-by-cycle limit threshold voltage given at IPK pin, in boost modeRIPK = 40 kΩ, VDIR < 1 V38.54862.25mV/V
OVERVOLTAGE PROTECTION (OVPA, OVPB)
OVP thresholdOVP voltage rising1.151.1851.22V
OVPHYSOVP hysteresis (falling edge)100mV
OVPA and OVPB glitch filter5µs
ROVPAInternal OVPA pullup resistorVINX to OVPA impedance3
ROVPBInternal OVPB pullup resistorCSB1 to OVPB impedance, VUVLO > 2.6 V1
OSCILLATOR (OSC)
Oscillator frequency 1ROSC = 40 kΩ, SYNCIN open90100110kHz
Oscillator frequency 2ROSC = 10 kΩ, SYNCIN open335375410kHz
VOSCOSC pin DC voltage1.25V
SYNCIN
VSYNIHSYNCIN input threshold for high state2V
VSYNIL SYNCSYNCIN input threshold for low state1V
Internal pulldown impedanceVSYNCIN = 2.5 V100kΩ
Delay to establish synchronization0.8 × FOSC < FSYNCIN < 1.2 × FOSC200µs
SYNCOUT
VSYNOHSYNCOUT high state2.5V
VSYNOLSYNCOUT low state0.4V
Sourcing current when SYNCOUT in high stateVSYNCOUT = 2.5 V1mA
SYNCOUT pulse width240300370ns
SYNCOUT phase delay configurationsVOPT > 2 V90Degree
VOPT < 1 V120
RSYNCOUTCircuit breaker signatureUse circuit breaker function and fault detection at start-upOPENkΩ
Do not use circuit breaker function or disable fault detection at start-up10
BOOTSTRAP (HB1, HB2)
VHB-UVBootstrap undervoltage threshold(VHB – VSW) voltage rising5.76.57.3V
VHB-UV-HYSHysteresis0.5V
IHB-LKBootstrap quiescent currentVHB – VSW = 10 V, VHO – VSW = 0 V50µA
HIGH-SIDE GATE DRIVERS (HO1, HO2)
VOLHHO low-state output voltageIHO = 100 mA0.1V
VOHHHO high-state output voltageIHO = –100 mA, VOHH = VHB – VHO0.15V
HO rise time (10% to 90% pulse magnitude)CLD = 1000 pF5ns
HO fall time (90% to 10% pulse magnitude)CLD = 1000 pF4ns
IOHHHO peak source currentVHB – VSW = 10 V4A
IOLHHO peak sink currentVHB – VSW = 10 V5A
LOW-SIDE GATE DRIVERS (LO1, LO2)
VOLLLO low-state output voltageILO = 100 mA0.1V
VOHLLO high-state output voltageILO = –100 mA, VOHL = VVCC – VLO0.15V
LO rise time (10% to 90% pulse magnitude)CLD = 1000 pF5ns
LO fall time (90% to 10% pulse magnitude)CLD = 1000 pF4ns
IOHLLO peak source current4A
IOLLLO peak sink current5A
INTERLEAVE PHASE DELAY FROM CH-2 To CH-1 (OPT)
VOPTLOPT input low state1V
VOPTHOPT input high state2V
HO2 on-time rising edge versus HO1 on-time rising edge, or LO2 on-time rising edge versus LO1 on-time rising edgeVOPT > 2 V for 2, 4, 6, and 8 phases175180185Degrees
VOPT < 1 V for 3 phases235240245
Internal pulldown impedance1
DEAD TIME (DT)
tDTLO falling edge to HO rising edge delayRDT = 7.5 kΩ40ns
tDTHO falling edge to LO rising edge delayRDT = 7.5 kΩ40ns
VDTDC voltage level for programming1.25V
VDTDC voltage for adaptive dead time scheme only (short DT to VCCA)VCCAV
VADPTHO-SW or LO-GND voltage threshold to enable cross output for adaptive dead time schemeVVCC > 9 V, (VHB – VSW) > 8 V, HO or LO voltage falling1.5V
tADPTLO falling edge to HO rising edge delayVDT = VVCC36ns
tADPTHO falling edge to LO rising edge delayVDT = VVCC41ns
SOFT START (SS)
ISSSS charging current sourceVSS = 0 V25µA
VSS-OFFSSS to PWM comparator offsetSS – PWM comparator noninverting input1V
RSSSS discharge device RDS(on)VSS = 2 V30
VSS_LOWSS discharge completion thresholdOnce it is discharged by internal logic0.23V
DIODE EMULATION
Current zero cross thresholdCurrent sense voltage0mV
CKT BREAKER CONTROL (BRKG, BRKS)
IBRKGSourcing currentnFAULT = 5 V, VVIN = 24 V, VBRKS = 12 V275330375µA
VBRK-CLPVoltage clampnFAULT= 5 V, VVIN = 48 V, VBRKS = 12 V914V
RBRK-SINKSinking capabilitynFAULT = 0 V20
VREADYBRKG to BRKS voltage threshold to indicate readiness for operationRising edge6.58.5V
IBRKG-LEAKBRKG leakage currentnFAULT= 5 V, VVIN – VBRKS = 0 V,
VBRKG – VBRKS = 10 V
10µA
FAULT ALARM (nFAULT)
In normal operation, no fault45V
Internal pull-up impedance for normal operation30kΩ
Internal pull-down FET RDS(on) after fault detected125
External pull-down voltage threshold for IC shutdown1V
tFAULTExternal pul-ldown glitch filter2µs
td1_FAULTDelay time of nFAULT pull-down below 1 V to (VBRKG – VBRKS) < 1.5 V5µs
td2_FAULTStart-up fault detection durationVUVLO > 2.6 V, VVCC > 9 V3ms
THERMAL SHUTDOWN
TSDThermal shutdown175°C
TSD-HYSThermal shutdown hysteresis25°C
All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Typical values correspond to TJ = 25°C.
Minimum and maximum limits apply over the –40°C to 125°C junction temperature range.