ZHCSEK4E December   2015  – August 2022 LMX2582

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  Channel Divider
      8. 7.3.8  Output Distribution
      9. 7.3.9  Output Buffer
      10. 7.3.10 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2582 Register Map – Default Values
        1. 7.6.1.1 Register Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2  Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3  Input Pin Configuration
      4. 8.1.4  Using the OSCin Doubler
      5. 8.1.5  Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6  Designing for Output Power
      7. 8.1.7  Current Consumption Management
      8. 8.1.8  Decreasing Lock Time
      9. 8.1.9  Modeling and Understanding PLL FOM and Flicker Noise
      10. 8.1.10 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 术语表
  10. 10Mechanical, Packaging, and Orderable Information

LMX2582 Register Map – Default Values

Figure 7-5 Register Table
REG23222120191817161514131211109876543210
R/WADDRESS[6:0]DATA [15:0]
0R/W000000000LD_EN0001FCAL_HPFD_ADJFCAL_LPFD_ADJACAL_ENFCAL_ENMUXOUT_SELRESETPOWERDOWN
1R/W00000010000100000001CAL_CLK_DIV
2R/W00000100000010100000000
4R/W0000100ACAL_CMP_DLY01000011
7R/W00001110010100010110010
8R/W000100000VCO_IDAC_OVR10VCO_CAPCTRL_OVR0010000100
9R/W00010010000OSC_2X0REF_EN100000010
10R/W00010100001MULT1011000
11R/W00010110000PLL_R1000
12R/W00011000111PLL_R_PRE
13R/W00011010CP_EN00000 0000000PFD_CTL
14R/W00011100000CP_IDNCP_IUPCP_ICOARSE
19R/W00100110000VCO_IDAC101
20R/W00101000000000ACAL_VCO_IDAC_STRT
22R/W001011000100011VCO_CAPCTRL
23R/W00101111FCAL_VCO_SEL_STRTVCO_SELVCO_SEL_FORCE0001000010
24R/W00110000000010100001001
25R/W00110010000000000000000
28R/W00111000010100100100100
29R/W00111010000000010000100
30R/W001111000000MASH_DITHER00VTUNE_ADJ110100
31R/W001111100000VCO_DISTB_PDVCO_DISTA_PD0CHDIV_DIST_PD0000001
32R/W01000000010000100001010
33R/W01000010010101000001010
34R/W01000101100001111CHDIV_EN01010
35R/W0100011000CHDIV_SEG2CHDIV_SEG3_ENCHDIV_SEG2_EN0011CHDIV_SEG1CHDIV_SEG1_EN1
36R/W01001000000CHDIV_DISTB_ENCHDIV_DISTA_EN000CHDIV_SEG_SELCHDIV_SEG3
37R/W0100101010PLL_N_PRE000000000000
38R/W0100110000PLL_N0
39R/W010011110PFD_DLY00000100
40R/W0101000PLL_DEN[31:16]
41R/W0101001PLL_DEN[15:0]
42R/W0101010MASH_SEED[31:16]
43R/W0101011MASH_SEED[15:0]
44R/W0101100PLL_NUM[31:16]
45R/W0101101PLL_NUM[15:0]
46R/W010111000OUTA_POWOUTB_PDOUTA_PD100MASH_ORDER
47R/W0101111000OUTA_MUX00011OUTB_POW
48R/W011000000000011111111OUTB_MUX
59R/W01110110000000000MUXOUT_HDRV00000
61R/W0111101000000000000000LD_TYPE
62R/W01111100000000000000000
64R/W1000000000000ACAL_FASTFCAL_FASTAJUMP_SIZE1FJUMP_SIZE
68 R 1 0 0 0 1 0 0 0 0 0 0 0 rb_LD_VTUNE 0 rb_VCO_SEL 0 0 0 0 0
69 R 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 rb_VCO_CAPCTRL
70 R 1 0 0 0 1 1 0 0 0 0 0 0 0 0 rb_VCO_DACISET