ZHCSEG6F December   2015  – May 2025 TCAN330 , TCAN330G , TCAN332 , TCAN332G , TCAN334 , TCAN334G , TCAN337 , TCAN337G

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5.   Device Options
  6. 4Pin Configuration and Functions
  7. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
    8. 5.8 Typical Characteristics, TCAN330 Receiver
    9. 5.9 Typical Characteristics, TCAN330 Driver
  8.   Parameter Measurement Information
  9. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 TXD Dominant Timeout (TXD DTO)
      2. 6.3.2 RXD Dominant Timeout (RXD DTO)
      3. 6.3.3 Thermal Shutdown
      4. 6.3.4 Undervoltage Lockout and Unpowered Device
      5. 6.3.5 Fault Pin (TCAN337)
      6. 6.3.6 Floating Pins
      7. 6.3.7 CAN Bus Short Circuit Current Limiting
      8. 6.3.8 ESD Protection
      9. 6.3.9 Digital Inputs and Outputs
    4. 6.4 Device Functional Modes
      1. 6.4.1 CAN Bus States
      2. 6.4.2 Normal Mode
      3. 6.4.3 Silent Mode
      4. 6.4.4 Standby Mode with Wake
      5. 6.4.5 Bus Wake via RXD Request (BWRR) in Standby Mode
      6. 6.4.6 Shutdown Mode
      7. 6.4.7 Driver and Receiver Function Tables
  10. 7Application Information Disclaimer
    1. 7.1 Application Information
      1. 7.1.1 Bus Loading, Length and Number of Nodes
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 CAN Termination
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 System Examples
      1. 7.3.1 ISO11898 Compliance of TCAN33x Family of 3.3V CAN Transceivers Introduction
      2. 7.3.2 Differential Signal
      3. 7.3.3 Common-Mode Signal and EMC Performance
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  11.   Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 商标
    4. 8.4 静电放电警告
    5. 8.5 术语表
  12. 8Revision History
  13. 9Mechanical, Packaging, and Orderable Information

6.3.2 RXD Dominant Timeout (RXD DTO)

All devices have a RXD DTO circuit that prevents a bus stuck dominant fault from permanently driving the RXD output dominant (low) when the bus is held dominant longer than the timeout period tRXD_DTO. The RXD DTO timer starts on a falling edge on RXD (bus going dominant). If no rising edge (bus returning recessive) is seen before the timeout constant of the circuit expires (tRXD_DTO), the RXD pin returns high (recessive). The RXD output is re-activated to mirror the bus receiver output when a recessive signal is seen on the bus, clearing the RXD dominant timeout. The CAN bus pins are biased to the recessive level during a RXD DTO.