ADS54J60 双通道 16 位 1.0GSPS 模数转换器

1 特性

• 16 位分辨率、双通道、1GSPS ADC
• 本底噪声：–159dBFS/Hz
• 频谱性能（f_IN = 170MHz，–1dBFS）：
  • 信噪比 (SNR)：70dBFS
  • 噪声频谱密度 (NSD)：–157dBFS/Hz
  • SFDR：86dBc（包括交错音调）
  • SFDR：89dBc（不包括 HD2、HD3 和交错音调）
• 频谱性能（f_IN = 350MHz，–1dBFS）：
  • SNR：67.5dBFS
  • NSD：–154.5dBFS/Hz
  • SFDR：75dBc
  • SFDR：85dBc（不包括 HD2、HD3 和交错音调）
• 通道隔离：f_IN = 170MHz 时为 100dBc
• 输入满标度：1.9V_PP
• 输入带宽 (3dB)：1.2GHz
• 片上抖动
• 集成宽带 DDC 块
• 支持子类 1 的 JESD204B 接口：
  • 10.0Gbps 时每个 ADC 具有 2 条信道
  • 5.0Gbps 时每个 ADC 具有 4 条信道
  • 支持多芯片同步
• 功耗：1GSPS 时为 1.35W/通道
• 封装：72 引脚 VQFNP (10mm × 10mm)

2 应用

• 雷达和天线阵列
• 无线宽带
• 电缆 CMTS、DOCSIS 3.1 接收器
• 通信测试设备
• 微波接收器
• 软件定义无线电 (SDR)
• 数字转换器
• 医疗成像和诊断

3 说明

ADS54J60 是一款低功耗、高带宽 16 位、1.0GSPS 双通道模数转换器 (ADC)。该器件经设计具有高信噪比 (SNR)，可提供 -159dBFS/Hz 的噪底，从而 协助应用在宽瞬时带宽内 实现最高动态范围。该器件支持 JESD204B 串行接口，数据传输速率高达 10Gbps，每个 ADC 可支持 2 或 4 条通道。已缓冲模拟输入在大大减少采样保持毛刺脉冲能量的同时，在宽频率范围内提供统一的输入阻抗。可选择将每个 ADC 通道连接至数字下变频器 (DDC) 模块。ADS54J60 以超低功耗在宽输入频率范围内提供出色的无杂散动态范围 (SFDR)。

JESD204B 接口减少了接口线路数，从而实现高系统集成度。内部锁相环 (PLL) 会将 ADC 采样时钟加倍，以获得串行化各通道的 16 位数据时所使用的位时钟。

1. 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

170MHz 输入信号的 FFT

4 修订历史记录

Changes from C Revision (January 2017) to D Revision

• Changed 170MHz 输入信号的 FFT 图Go
• Changed the description of the CLKINM, CLKINP, SYSREFM, SYSREFP, and PDN pins in Pin Functions tableGo
• Changed typical values across parameters in AC Characteristics tableGo
• Changed value of A_IN from –1 dBFS to –3 dBFS in 470 MHz test condition across all parameters in AC Characteristics tableGo
• Added ENOB parameter to AC Characteristics table Go
• Changed the first footnote in Timing Characteristics tableGo
• Changed the typical value of FOVR latency from 18 + 4 ns to 18 in Timing Characteristics tableGo
• Changed parameter name from t_PD to t_PDI in Timing Characteristics tableGo
• Changed FFT for 170-MHz Input Signal figureGo
• Changed FFT for 470-MHz Input Signal at –3 dBFS figure, title, and conditionsGo
• Changed conditions of FFT for 720-MHz Input Signal at –6 dBFS figureGo
• Changed Spurious-Free Dynamic Range vs Input Frequency figureGo
• Changed DDC Block figureGo
• Deleted register address 53 from Register Address for Power-Down Modes tableGo
• Added last sentence to Step 4 in Serial Register Readout: Analog Bank sectionGo
• Added last sentence to Step 4 in Serial Register Readout: JESD Bank section Go
• Added SDOUT Timing Diagram figureGo
• Deleted unrelated patterns in in JESD204B Test Patterns sectionGo
• Changed Serial Interface Registers figureGo
• Added register addresses 1h and 2h and their descriptions to GENERAL REGISTERS in Register Map sectionGo
• Changed the name of MASTER PAGE (80h) to MASTER PAGE (ANALOG BANK PAGE SEL= 80h in Register Map tableGo
• Changed register 53h and 54h, and their descriptions to MASTER PAGE (ANALOG BANK PAGE SEL = 80h) in Register Map sectionGo
• Changed the name of ADC PAGE (0Fh) to ADC PAGE (ANALOG BANK PAGE SEL= 0Fh) in Register Map tableGo
• Changed the name of MAIN DIGITAL PAGE (6800h) to MAIN DIGITAL PAGE (JESD BANK PAGE SEL=6800h) in Register Map tableGo
• Changed bit 5, register 4E of MAIN DIGITAL PAGE (JESD BANK PAGE SEL = 6800h) from 0 to IMPROVE IL PERFGo
• Changed the name of JESD DIGITAL PAGE (6900h) to JESD DIGITAL PAGE (JESD BANK PAGE SEL=6900h) in Register Map tableGo
• Changed the name of JESD ANALOG PAGE (6A00h) to JESD ANALOG PAGE (JESD BANK PAGE SEL=6A00h) in Register Map tableGo
• Changed bit 1, register 12 of JESD ANALOG PAGE (6A00h) from 0 to ALWAYS WRITE 1Go
• Changed bits 5 and 3, register 17 of JESD ANALOG PAGE (JESD BANK PAGE SEL = 6A00h) from 0 to LANE PDN 1 and from 0 to LANE PDN 0 respectivelyGo
• Added OFFSET READ Page and OFFSET LOAD Page registers to Register Map tableGo
• Added ADS54J60 Access Type Codes table, deleted legends from Register Descriptions sectionGo
• Added register 1h and 2h to Register Descriptions section Go
• Changed description of Registers 3h and 4h (address = 3h and 4h) in General Registers PageGo
• Changed description of bit 0 in Register 4Fh (address = 4Fh), Master Page (080h)Go
• Changed the description of registers 53h and 54hGo
• Changed 9.5 dB to 12 dB in description of bits 6-0 in Register 44h (address = 44h), Main Digital Page (6800h)Go
• Changed bit 5 from 0 the IMPROVE IL PERF and changed Register 4Eh Field Descriptions table in Register 4Eh (address = 4Eh), Main Digital Page (6800h)Go
• Changed bit 1 from 0 to ALWAYS WRITE 1 in Register 12h (address = 12h), JESD Analog Page (6A00h)Go
• Changed bit 1 from ALWAYS WRITE 1 to 0 in register 15h bit register Go
• Added x (where x = 0, 2, or 3) to bits 7-2 in Register 13h-15h Field Descriptions table of Registers 13h-15h (address = 13h-15h), JESD Analog Page (6A00h)Go
• Changed bit 6 from W to R/W, bit 5 from 0 to LANE PDN 1 and from W to R/W, and changed bit 3 from 0 to LANE PDN 0 and from W to R/W in Register 17h bit register table of Register 17h (address = 17h), JESD Analog Page (6A00h)Go
• Changed bits 5-0 of Register 17h Field Descriptions table in Register 17h (address = 17h), JESD Analog Page (6A00h)Go
• Added Offset Read Page Register and Offset Load Page Register sections to Register Descriptions sectionGo
• Added DC Offset Correction Block in the ADS54J60 sectionGo
• Changed ±512 codes to ±1024 codes in DC Offset Correction Block in the ADS54J60 sectionGo
• Added Idle Channel Histogram sectionGo
• Added transformer TC1-1-13M+ to Transformer-Coupled Circuits sectionGo
• Added note to Layout Guidelines sectionGo

Changes from B Revision (August 2015) to C Revision

• Changed 频谱性能特性要点的 最后一个 子要点中的 SFDR 值Go
• Changed 器件信息表Go
• Added CDM row to ESD Ratings tableGo
• Changed the minimum value for the input clock frequency in the Recommended Operating Conditions table Go
• Added minimum value to the ADC sampling rate parameter in the Electrical Characteristics tableGo
• Added 720 -MHz test condition rows to SNR, NSD, SINAD, SFDR, HD2, HD3, Non HD2, HD3, THD, and SFDR_IL parameters of AC Characteristics tableGo
• Changed typical specification of SFDR parameter in AC Characteristics tableGo
• Changed Sample Timing, Aperture jitter parameter typical specification in Timing Characteristics sectionGo
• Added the FOVR latency parameter to the Timing Characteristics tableGo
• Added FFT for 720-MHz Input Signal at –6 dBFS figureGo
• Added Typical Characteristics: Contour sectionGo
• Changed Overview section Go
• Changed Functional Block Diagram section: changed Control and SPI block and added dashed outline to FOVR tracesGo
• Added Figure 60 and text reference to Analog Inputs sectionGo
• Changed SYSREF Signal section: changed Table 4 and added last paragraphGo
• Added SYSREF Not Present (Subclass 0, 2) sectionGo
• Changed the number of clock cycles in the Fast OVR sectionGo
• Changed Table 10 and Table 11Go
• Changed Table 12 and Table 13Go
• Deleted Lane Enable with Decimation subsection Go
• Added the Program Summary of DDC Modes and JESD Link Configuration tableGo
• Added Figure 84 to Register Maps sectionGo
• Changed Table 15Go
• Deleted register 39h, 3Ah, and 56h Go
• Changed Example Register Writes sectionGo
• Updated register descriptions Go
• Added Table 54Go
• Deleted row for bit 1 in Table 64 as bit 1 is included in last table row Go
• Changed Table 75Go
• Changed internal aperture jitter value in SNR and Clock Jitter sectionGo
• Changed Figure 141Go
• Changed Power Supply Recommendations section Go
• Added the Power Sequencing and Initialization sectionGo
• Added 文档支持 和接收文档更新通知 部分Go

Changes from A Revision (May 2015) to B Revision

• 已投入量产Go

5 Device Comparison Table

6 Pin Configuration and Functions

RMP Package

72-Pin VQFNP

Top View

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 AC Characteristics

7.7 Digital Characteristics

7.8 Timing Requirements

Figure 1. SYSREF Timing

Figure 2. Sample Timing Requirements Diagram

7.9 Typical Characteristics

SNR = 71 dBFS; SFDR = 86 dBc; IL spur = 94 dBc; non HD2, HD3 spur = 89 dBc

Figure 3. FFT for 10-MHz Input Signal

SNR = 69.8 dBFS; SFDR = 88 dBc; IL spur = 86 dBc; non HD2, HD3 spur = 89 dBc

Figure 5. FFT for 170-MHz Input Signal

SNR = 68 dBFS; SFDR = 77 dBc; IL spur = 84 dBc; non HD2, HD3 spur = 85 dBc

Figure 7. FFT for 300-MHz Input Signal

SNR = 67.9 dBFS; SFDR = 74 dBc; IL spur = 82 dBc; non HD2, HD3 spur = 89 dBc

Figure 9. FFT for 470-MHz Input Signal at –3 dBFS

fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –7 dBFS, IMD3 = 88 dBFS

Figure 11. FFT for Two-Tone Input Signal (–7 dBFS)

fIN1 = 365 MHz, fIN2 = 370 MHz, each tone at –7 dBFS, IMD3 = 80 dBFS

Figure 13. FFT for Two-Tone Input Signal (–7 dBFS)

fIN1 = 465 MHz, fIN2 = 470 MHz, each tone at –7 dBFS, IMD3 = 75 dBFS

Figure 15. FFT for Two-Tone Input Signal (–7 dBFS)

fIN1 = 185 MHz, fIN2 = 190 MHz

Figure 17. Intermodulation Distortion vs
Input Tone Amplitude

fIN1 = 465 MHz, fIN2 = 470 MHz

Figure 19. Intermodulation Distortion vs
Input Tone Amplitude

Figure 21. IL Spur vs Input Frequency

fIN = 170 MHz

Figure 23. Signal-to-Noise Ratio vs
AVDD Supply and Temperature

fIN = 350 MHz

Figure 25. Signal-to-Noise Ratio vs
AVDD Supply and Temperature

fIN = 170 MHz

Figure 27. Signal-to-Noise Ratio vs
DVDD Supply and Temperature

fIN = 350 MHz

Figure 29. Signal-to-Noise Ratio vs
DVDD Supply and Temperature

fIN = 170 MHz

Figure 31. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature

fIN = 350 MHz

Figure 33. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature

Figure 35. Signal-to-Noise Ratio vs
Gain and Input Frequency

Figure 37. Maximum Supported Amplitude vs Frequency

fIN = 350 MHz

Figure 39. Performance vs Input Amplitude

fIN = 350 MHz

Figure 41. Performance vs Sampling Clock Amplitude

fIN = 350 MHz

Figure 43. Performance vs Clock Duty Cycle

fIN = 170 MHz , AIN = –1 dBFS, SINAD = 67 dBFS, SFDR = 79 dBc, fPSRR = 5 MHz, APSRR = 25 mVPP, amplitude of fIN – fPSRR = –74 dBFS, amplitude of fIN + fPSRR = –76 dBFS

Figure 45. Power-Supply Rejection Ratio FFT for
Test Signals on the AVDD Supply

fIN = 170 MHz , AIN = –1 dBFS, fCMRR = 5 MHz, ACMRR = 50 mVPP, SINAD = 69.1 dBFS, SFDR = 86 dBc, amplitude of fIN ± fCMRR= –80 dBFS

Figure 47. Common-Mode Rejection Ratio FFT

Figure 49. Power vs Temperature

SNR = 75.2 dBFS, SFDR = 90 dBc

Figure 51. FFT for 170-MHz Input Signal in
Decimate-by-4 Mode

SNR = 69.6 dBFS, SFDR = 84 dBc

Figure 53. FFT for 450-MHz Input Signal in
Decimate-by-4 Mode

SNR = 68.3 dBFS, SFDR = 80 dBc

Figure 55. FFT for 350-MHz Input Signal in
Decimate-by-2 Mode

SNR = 70.3 dBFS; SFDR = 90 dBc; IL spur = 95 dBc; non HD2, HD3 spur = 94 dBc

Figure 4. FFT for 140-MHz Input Signal

SNR = 68.9 dBFS; SFDR = 85 dBc; IL spur = 85 dBc; non HD2, HD3 spur = 86 dBc

Figure 6. FFT for 230-MHz Input Signal

SNR = 66.7 dBFS; SFDR = 71 dBc; IL spur = 87 dBc; non HD2, HD3 spur = 78 dBc

Figure 8. FFT for 370-MHz Input Signal

SNR = 66.3 dBFS, SINAD = 65.3 dBFS, THD = 70 dBc, IL spur = 84 dBc, SFDR = 73 dBc, non HD2, HD3 spur = 90 dBFS

Figure 10. FFT for 720-MHz Input Signal at –6 dBFS

fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –36 dBFS, IMD3 = 106 dBFS

Figure 12. FFT for Two-Tone Input Signal (–36 dBFS)

fIN1 = 365 MHz, fIN2 = 370 MHz, each tone at –36 dBFS, IMD3 = 105 dBFS

Figure 14. FFT for Two-Tone Input Signal (–36 dBFS)

fIN1 = 465 MHz, fIN2 = 470 MHz, each tone at –36 dBFS, IMD3 = 106 dBFS

Figure 16. FFT for Two-Tone Input Signal (–36 dBFS)

fIN1 = 365 MHz, fIN2 = 370 MHz

Figure 18. Intermodulation Distortion vs
Input Tone Amplitude

Figure 20. Spurious-Free Dynamic Range vs
Input Frequency

Figure 22. Signal-to-Noise Ratio vs Input Frequency

fIN = 170 MHz

Figure 24. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature

fIN = 350 MHz

Figure 26. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature

fIN = 170 MHz

Figure 28. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature

fIN = 350 MHz

Figure 30. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature

fIN = 170 MHz

Figure 32. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature

fIN = 350 MHz

Figure 34. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature

Figure 36. Spurious-Free Dynamic Range vs
Gain and Input Frequency

fIN = 170 MHz

Figure 38. Performance vs Input Amplitude

fIN = 170 MHz

Figure 40. Performance vs Sampling Clock Amplitude

fIN = 170 MHz

Figure 42. Performance vs Clock Duty Cycle

fIN = 170 MHz

Figure 44. Power-Supply Rejection Ratio vs
Test Signal Frequency

fIN = 170 MHz

Figure 46. Common-Mode Rejection Ratio vs
Test Signal Frequency

Figure 48. Power vs Sampling Speed

SNR = 76.4 dBFS, SFDR = 99 dBc

Figure 50. FFT for 60-MHz Input Signal in
Decimate-by-4 Mode

SNR = 72.8 dBFS, SFDR = 91 dBc

Figure 52. FFT for 300-MHz Input Signal in
Decimate-by-4 Mode

SNR = 71.9 dBFS, SFDR = 89 dBc

Figure 54. FFT for 170-MHz Input Signal in
Decimate-by-2 Mode

7.10 Typical Characteristics: Contour

Figure 56. Spurious Free Dynamic Range

Figure 57. Signal-to-Noise-Ratio

8 Detailed Description