RF430CL330H 动态近场通信 (NFC) 接口应答器
- ZHCSB37C November 2012 – November 2014 RF430CL330H
  
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RF430CL330H 动态近场通信 (NFC) 接口应答器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 器件概述

1.1 特性

NFC 标签类型 4
符合 ISO14443B 标准的 13.56MHz (RF) 接口支持高达 848kbps
串行外设接口 (SPI) 或 I²C 接口将近场通信数据交换格式 (NDEF) 消息写入内部 SRAM 并从中读取此消息
为 NDEF 消息提供 3KB SRAM
NDEF 结构的自动校验
中断寄存器和输出引脚以表示 NDEF 读取或写入完成

1.2 应用

Bluetooth® 配对
Wi-Fi® 配置
诊断接口
传感器接口

1.3 说明

德州仪器 (TI) 动态 NFC 接口应答器 RF430CL330H 是一款 NFC 标签类型 4 器件，可结合一个无线 NFC 接口和一个有线 SPI 或 I²C 接口将器件连接到主机。 SRAM 中的 NDEF 消息可通过集成的 SPI 或 I²C 串行通信接口读写，也可通过支持高达 848kbps 速率的集成 ISO14443B 标准射频接口无线访问或更新。

这种工作方式可以直观地简化备用载波的 NFC 连接切换，例如，只需轻轻点击即可完成蓝牙、低功耗蓝牙 (BLE) 和 Wi-Fi 配对过程或验证过程。作为一个常见 NFC 接口，RF430CL330H 使得终端设备能够与启用 NFC 的智能手机、平板电脑和笔记本电脑这类快速增长的基础设施进行通信。

Table 1-1 器件信息⁽¹⁾

器件型号	封装	封装尺寸⁽²⁾
RF430CL330HPW	TSSOP (14)	5mm x 4.4mm
RF430CL330HRGT	VQFN (16)	3mm x 3mm

(1) 要获得所有可用器件的最新部件、封装和订购信息，请参见Section 7中的封装选项附录或浏览 TI 网站 www.ti.com.cn。

(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见Section 7中的机械数据。

1.4 典型应用图

Figure 1-1 显示了 RF430CL330H 器件的典型应用图。

Figure 1-1 典型应用

2 修订历史记录

Changes from B Revision (June 2014) to C Revision

已在器件信息表中添加 RGT 封装Go
Added RGT package pinoutGo
Added RGT package to Table 3-1Go
Added Section 4.8Go

3 Terminal Configuration and Functions

Figure 3-1 shows the pin assignments for the PW package.

Figure 3-1 14-Pin PW Package (Top View)

Figure 3-2 shows the pin assignments for the RGT package.

Figure 3-2 16-Pin RGT Package (Top View)

Table 3-1 Terminal Functions

TERMINAL			I/O	DESCRIPTION
NAME	NO.
NAME	PW	RGT
VCC	1	15	PWR	3.3-V power supply
ANT1	2	1	RF	Antenna input 1
ANT2	3	2	RF	Antenna input 2
RST	4	3	I	Reset input (active low)
E0 (TMS)	5	4	I	I²C address select 0 SPI mode select 0 (JTAG test mode select)
E1 (TDO)	6	5	I (O)	I²C address select 1 SPI mode select 1 (JTAG test data output)
E2 (TDI)	7	6	I	I²C address select 2 (JTAG test data in)
INTO (TCK)	8	7	O	Interrupt output (JTAG test clock)
SCMS/ CS	9	8	I	Serial Communication Mode Select (during device initialization) Chip select (in SPI mode)
SCK	10	9	I	SPI clock input (SPI mode)
SO/SCL	11	10	I/O	SPI slave out (SPI mode) I²C clock (I²C mode)
SI/SDA	12	11	I/O	SPI slave in (SPI mode) I²C data (I²C mode)
VCORE	13	12	PWR	Regulated core supply voltage
VSS	14	13	PWR	Ground supply
NC	-	14, 16		Leave open, No connection

NOTE:

For recommended capacitance values, see Recommended Operating Conditions.

Figure 3-3 Example Application Diagram (I²C Operation) (PW Package Shown)

NOTE:

For recommended capacitance values, see Recommended Operating Conditions.

Figure 3-4 Example Application Diagram (SPI Operation) (PW Package Shown)

4 Specifications

4.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
Voltage applied at V_CC referenced to V_SS (V_AMR)	-0.3	4.1	V
Voltage applied at V_ANT referenced to V_SS(V_AMR)	-0.3	4.1	V
Voltage applied to any pin (references to V_SS)	-0.3	V_CC + 0.3	V
Diode current at any device pin		±2	mA

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are referenced to VSS.

(3) For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

4.2 Handling Ratings

		MIN	MAX	UNIT
T_stg	Storage temperature range⁽³⁾	-40	125	°C

4.3 Recommended Operating Conditions

Typical values are specified at V_CC = 3.3 V and T_A = 25°C (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_CC	Supply voltage during program execution no RF field present	3.0	3.3	3.6	V
V_CC	Supply voltage during program execution with RF field present	2.0	3.3	3.6	V
V_SS	Supply voltage (GND reference)		0		V
T_A	Operating free-air temperature	-40		85	°C
C₁	Decoupling capacitor on V_CC⁽¹⁾		0.1		µF
C₂	Decoupling capacitor on V_CC⁽¹⁾		1		µF
C_VCORE	Capacitor on V_CORE⁽¹⁾	0.1	0.47	1	µF

(1) Low equivalent series resistance (ESR) capacitor

4.4 Recommended Operating Conditions, Resonant Circuit

		MIN	NOM	MAX	UNIT
f_c	Carrier frequency		13.56		MHz
V_{ANT_peak}	Antenna input voltage			3.6	V
Z	Impedance of LC circuit	6.5		15.5	kΩ
L_RES	Coil inductance⁽²⁾		2.66		µH
C_RES	Total resonance capacitance⁽²⁾ C_RES = C_IN+C_Tune		51.8		pF
C_Tune	External resonance capacitance		C_RES – C_IN⁽¹⁾		pF
QT	Tank quality factor		30

(1) For C_IN refer to Section 4.12.

(2) The coil inductance of the antenna L_RES together with the external capacitance C_Tune plus the device internal capacitance C_IN is a resonant circuit. The resonant frequency of this LC circuit must be close to the carrier frequency f_c:
f_RES = 1 / [2π(L_RESC_RES)^1/2] = 1 / [2π(L_RES(C_IN + C_Tune))^1/2] ≈ f_c

4.5 Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		V_CC	TYP	MAX	UNIT
I_CC(SPI)	SPI, f_SCK,MAX, SO = Open, Writing into NDEF memory	3.3 V	250		µA
I_CC(I2C)	I²C, 400 kHz, Writing into NDEF memory	3.3 V	250		µA
I_{CC(RF enabled)}	RF enabled, no RF field present	3.3 V	40		µA
I_CC(Inactive)	Standby enable = 0, RF disabled, no serial communication	3.3 V	15		µA
I_CC(Standby)	Standby enable = 1, RF disabled, no serial communication	3.3 V	10	45	µA
ΔI_CC(StrongRF)	Additional current consumption with strong RF field present	3.0 V to 3.6 V		160	µA
I_{CC(RF,lowVCC)}	Current drawn from VCC < 3.0 V with RF field present (passive operation)	2.0 V to 3.0 V		0	µA

4.6 Digital Inputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		V_CC	MIN	TYP	MAX	UNIT
V_IL	Low-level input voltage				0.3× V_CC	V
V_IH	High-level input voltage		0.7× V_CC			V
V_HYS	Input hysteresis		0.1× V_CC			V
I_L	High-impedance leakage current	3.3 V	-50		50	nA
R_PU(RST)	Integrated RST pullup resistor		20	35	50	kΩ
R_PU(CS)	Integrated SCMS/CS pullup resistor (only active during initialization)		20	35	50	kΩ

4.7 Digital Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
V_OL	Output low voltage	I_OL = 3 mA	3 V		0.4	V
			3.3 V		0.4
			3.6 V		0.4
V_OH	Output high voltage	I_OH = -3 mA	3 V	2.6		V
			3.3 V	2.9
			3.6 V	3.2

4.8 Thermal Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER			VALUE	UNIT
θ_JA	Junction-to-ambient thermal resistance, still air⁽¹⁾	TSSOP-14 (PW)	116.0	°C/W
θ_JC(TOP)	Junction-to-case (top) thermal resistance⁽²⁾		45.1	°C/W
θ_JB	Junction-to-board thermal resistance⁽³⁾		57.6	°C/W
Ψ_JB	Junction-to-board thermal characterization parameter		57.0	°C/W
Ψ_JT	Junction-to-top thermal characterization parameter		4.6	°C/W
θ_JA	Junction-to-ambient thermal resistance, still air⁽¹⁾	VQFN-16 (RGT)	48.8	°C/W
θ_JC(TOP)	Junction-to-case (top) thermal resistance⁽²⁾		60.8	°C/W
θ_JB	Junction-to-board thermal resistance⁽³⁾		21.9	°C/W
Ψ_JB	Junction-to-board thermal characterization parameter		21.9	°C/W
Ψ_JT	Junction-to-top thermal characterization parameter		1.5	°C/W
θ_JC(BOT)	Junction-to-case (bottom) thermal resistance⁽⁴⁾		7.1	°C/W

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

4.9 Serial Communication Protocol Timings

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		MIN	TYP	MAX	UNIT
t_SPIvsI2C	Time after power-up or reset until SCMS/CS is sampled for SPI or I²C decision⁽¹⁾	1		10	ms
t_Ready	Time after power-up or reset until device is ready to communicate using SPI or I²C⁽²⁾			20	ms

(1) The SCMS/CS pin is sampled after t_SPIvsI2C(MIN) at the earliest and after t_SPIvsI2C(MAX) at the latest.

(2) The device is ready to communicate after t_Ready(MAX) at the latest.

4.10 I²C Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4-1)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
f_SCL	SCL clock frequency (with Master supporting clock stretching according to I²C standard, or when the device is not being addressed)		3.3 V	0	400	kHz
	SCL clock frequency (device being addressed by Master not supporting clock stretching)	write	3.3 V	0	120	kHz
		read	3.3 V	0	100	kHz
t_HD,STA	Hold time (repeated) START	f_SCL ≤ 100 kHz	3.3 V	4		µs
t_HD,STA	Hold time (repeated) START	f_SCL > 100 kHz	3.3 V	0.6		µs
t_SU,STA	Setup time for a repeated START	f_SCL ≤ 100 kHz	3.3 V	4.7		µs
t_SU,STA	Setup time for a repeated START	f_SCL > 100 kHz	3.3 V	0.6		µs
t_HD,DAT	Data hold time		3.3 V	0		ns
t_SU,DAT	Data setup time		3.3 V	250		ns
t_SU,STO	Setup time for STOP		3.3 V	4		µs
t_SP	Pulse duration of spikes suppressed by input filter		3.3 V	6.25	75	ns

Figure 4-1 I²C Mode Timing

4.11 SPI Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
f_SCK	SCK clock frequency	write	3.3 V	0	100	kHz
f_SCK	SCK clock frequency	read	3.3 V	0	110	kHz
t_HIGH,CS	CS high time		3.3 V	50		µs
t_SU,CS	CS setup time		3.3 V	25		µs
t_HD,CS	CS hold time		3.3 V	100		ns
t_HIGH	SCK high time		3.3 V	100		ns
t_LOW	SCK low time		3.3 V	100		ns
t_SU,SI	Data In (SI) setup time		3.3 V	50		ns
t_HD,SI	Data In (SI) hold time		3.3 V	50		ns
t_VALID,SO	Output (SO) valid		3.3 V	0	50	ns
t_HOLD,SO	Output (SO) hold time		3.3 V	0		ns

Figure 4-2 SPI Mode Timing

4.12 RF143B, Recommended Operating Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_DDH	Antenna rectified voltage	Peak voltage limited by antenna limiter	3.0	3.3	3.6	V
I_DDH	Antenna load current	RMS, without limiter current			100	µA
C_IN	Input capacitance	ANT1 to ANT2, 2 V RMS	31.5	35	38.5	pF

4.13 RF143B, ISO14443B ASK Demodulator

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		MIN	TYP	MAX	UNIT
DR₁₀	Input signal data rate 10% downlink modulation, 7% to 30% ASK, ISO1443B		106	848	kbps
m10	Modulation depth 10%, tested as defined in ISO10373	7		30	%

4.14 RF143B, ISO14443B-Compliant Load Modulator

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
f_PICC	Uplink subcarrier modulation frequency	0.2	1	MHz
V_{A_MOD}	Modulated antenna voltage, V_{A_unmod} = 2.3 V	0.5		V
V_SUB14	Uplink modulation subcarrier level, ISO14443B: H = 1.5 to 7.5 A/m	22/H^0.5		mV

4.15 RF143B, Power Supply

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_LIM	Limiter clamping voltage	I_LIM ≤ 70 mA RMS, f = 13.56 MHz	3.0		3.6	V_pk
I_LIM,MAX	Maximum limiter current				70	mA

5 Detailed Description

5.1 Functional Block Diagram

Figure 5-1 shows the functional block diagram.

Figure 5-1 Functional Block Diagram

5.2 Serial Communication Interface

A "dual-mode" serial communication interface supports either SPI or I²C communication. The serial interface allows writing and reading the internal NDEF memory as well as configuring the device operation.

5.3 SPI or I²C Mode Selection

The selection between I²C or SPI mode takes place during the power-up and initialization phase of the device based on the input level at pin SCMS/CS (see Table 5-1).

Table 5-1 SPI or I²C Mode Selection

Input Level at SCMS/CS During Initialization	Selected Serial Interface
0	I²C
1	SPI

During initialization, an integrated pullup resistor pulls SCMS/CS high, which makes SPI the default interface. To enable I²C, this pin must be tied low externally. The pullup resistor is disabled after initialization to avoid any current through the resistor during normal operation. In SPI mode, the pin reverts to its CS functionality after initialization.

5.4 Communication Protocol

The tag is programmed and controlled by writing data into and reading data from the address map shown in Table 5-2 via the serial interface (SPI or I²C).

Table 5-2 User Address Map

Range	Address	Size	Description
Registers	0xFFFE	2B	Control Register
	0xFFFC	2B	Status Register
	0xFFFA	2B	Interrupt Enable
	0xFFF8	2B	Interrupt Flags
	0xFFF6	2B	CRC Result (16-bit CCITT)
	0xFFF4	2B	CRC Length
	0xFFF2	2B	CRC Start Address
	0xFFF0	2B	Communication Watchdog Control Register
	0xFFEE	2B	Version
	0xFFEC	2B	Reserved
	0xFFEA	2B	Reserved
	0xFFE8	2B	Reserved
	0xFFE6	2B	Reserved
	0xFFE4	2B	Reserved
	0xFFE2	2B	Reserved
	0xFFE0	2B	Reserved
Reserved	0x4000 to 0xFFDF		Reserved
Reserved	0x0C00 to 0x3FFF	13KB	Reserved (for example, future extension of NDEF Memory size)
NDEF	0x0000 to 0x0BFF	3KB	NDEF Memory

NOTE

Crossing Range Boundaries

Crossing range boundaries causes writes to be ignored and reads to return undefined data.

5.5 I²C Protocol

A command is always initiated by the master by addressing the device using the specified I²C device address. The device address is a 7-bit I²C address. The upper 4 bits are hard-coded, and the lower 3 bits are programmable by the input pins E0 through E2.

Table 5-3 I²C Device Address

Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0	1	0	1	E2	E1	E0
MSB						LSB

To write data, the device is addressed using the specified I²C device address with R/W = 0, followed by the upper 8 bits of the first address to be written and the lower 8 bits of that address. Next (without a repeated start), the data to be written starting at the specified address is received. With each data byte received, the address is automatically incremented by 1. The write access is terminated by the STOP condition on the I²C bus.

RF430CL330H i2c_write_access_slas850.gif

Figure 5-2 I²C Write Access

To read data, the device is addressed using the specified I²C device address with R/W = 0, followed by the upper 8 bits of the first address to be read and then the lower 8 bits of that address. Next, a repeated start condition is expected with the I²C device address and R/W = 1. The device then transmit data starting at the specified address until a non-acknowledgment and a STOP condition is received.

Figure 5-3 I²C Read Access

The following figures show examples of I²C accesses to the Control register at address 0xFFFE.

RF430CL330H i2c_write_control_reg_example.png

Figure 5-4 I²C Access Example: Write of the Control Register at Address 0xFFFE With 0x00, 0x02 (RF Enable = 1)

RF430CL330H i2c_read_control_reg_example.png

Figure 5-5 I²C Access Example: Read of the Control Register at Address 0xFFFE, Responds With 0x00, 0x02 (RF Enable = 1)

5.5.1 BIP-8 Communication Mode With I²C

The BIP-8 communication mode is enabled by setting the BIP-8 bit in the General Control register. All communication after setting this bit uses the following conventions with exactly 2 address bytes (16-bit address) and 2 data bytes (16-bit data).

Table 5-4 Write Access

Master	Address Bits 15 to 8	Address Bits 7 to 0	Data at Addr + 0	Data at Addr + 1	BIP-8
Slave	n/a	n/a	n/a	n/a	n/a

The Bit-Interleaved Parity (BIP-8) is calculated using 16-bit address and 16-bit data. If the received BIP-8 does not match with received data no write will be performed. (The BIP-8 calculation does not include the I²C device address).

Table 5-5 Read Access

Master	Address Bits 15 to 8	Address Bits 7 to 0	n/a	n/a	n/a
Slave	n/a	n/a	Data at Addr + 0	Data at Addr + 1	BIP-8

For read access, the Bit-Interleaved Parity (BIP-8) is calculated using the received 16-bit address and the 2 transmitted data bytes, and it is transmitted back to the master. The BIP-8 does not include the device address.

5.6 SPI Protocol

The SPI communication mode (SCK idle state and clock phase) is selected by tying E0 and E1 to VSS or VCC according to Table 5-6.

Table 5-6 SPI Mode Selection

E1	E0	SPI Mode
0	0	SPI Mode 0 with CPOL = 0 and CPHA = 0 SCK idle state: 0 SI capture starts on the first edge: SI data is captured on the rising edge, and SO data is propagated on the falling edge.
0	1	SPI Mode 1 with CPOL = 0 and CPHA = 1 SCK idle state: 0 SI capture starts on the second edge: SI data is captured on the falling edge, and SO data is propagated on the rising edge.
1	0	SPI Mode 2 with CPOL = 1 and CPHA = 0 SCK idle state: 1 SI capture starts on the first edge: SI data is captured on the falling edge, and SO data is propagated on the rising edge.
1	1	SPI Mode 3 with CPOL = 1 and CPHA = 1 SCK idle state: 1 SI capture starts on the second edge: SI data is captured on the rising edge, and SO data is propagated on the falling edge.

An SPI communication is always initiated by the master by pulling the CS pin low.

To write data into the device, this is followed by the master sending a write command (0x02) followed by the upper 8 bits of the first address to be written and then the lower 8 bits of that address. Next, the data to be written starting at the specified address is received. With each data byte received, the address is automatically incremented by 1. The write access is terminated by pulling the CS pin high.

RF430CL330H spi_write_access_slas850.gif

Figure 5-6 SPI Write Access

To read data from the device, pulling the CS pin low is followed by the master sending a read command (0x03 or 0x0B) followed by the upper 8 bits of the first address to be read, the lower 8 bits of that address, and a dummy byte. The device responds with the data that is read starting at the specified address until the CS pin is pulled high.

RF430CL330H spi_read_access_cmd_0x03_slas850.gif

Figure 5-7 SPI Read Access (Command: 0x03 or 0x0B)

Commands other than write (0x02) and read (0x03 or 0x0B) are ignored. There is no difference in using the read command 0x03 or 0x0B.

Figure 5-8 and Figure 5-9 show examples of SPI accesses to the Control register at address 0xFFFE.

RF430CL330H spi_write_control_reg_example.png

Figure 5-8 SPI Access Example: Write of the Control Register at Address 0xFFFE With 0x00, 0x02 (RF Enable = 1)

RF430CL330H spi_read_control_reg_example.png

Figure 5-9 SPI Access Example: Read of the Control Register at Address 0xFFFE, Responds With 0x00, 0x02 (RF Enable = 1)

5.6.1 BIP-8 Communication Mode With SPI

Table 5-7 Write Access

SI	Command: Write	Address Bits 15 to 8	Address Bits 7 to 0	Data at Addr + 0	Data at Addr + 1	BIP-8
SO	n/a	n/a	n/a	n/a	n/a	n/a

Table 5-8 Read Access

SI	Command: Read	Address Bits 15 to 8	Address Bits 7 to 0	Dummy Byte	n/a	n/a	n/a
SO	n/a	n/a	n/a	n/a	Data at Addr + 0	Data at Addr + 1	BIP-8

For read access the Bit-Interleaved Parity (BIP-8) is calculated using the received 16-bit address, the received dummy byte and the 2 transmitted data bytes and transmitted back to the master. It does not include the read-command byte.

5.7 Registers

NOTE

Endianness

All 16-bit registers are little-endian: the least significant byte with bits 7-0 is at the lowest address (and this address is always even). The most significant byte with bits 15-8 is at the highest address (always odd).

5.7.1 General Control Register

Table 5-9 General Control Register

Addr:	15	14	13	12	11	10	9	8
0xFFFF	Reserved
Addr:	7	6	5	4	3	2	1	0
0xFFFE	Reserved	Standby Enable	BIP-8	INTO Drive	INTO High	Enable INT	Enable RF	SW-Reset

Table 5-10 General Control Register Description

Bit	Field	Type	Description
0	SW-Reset	W	0b = Always reads 0. 1b = Resets the device to default settings and clears memory. The serial communication is restored after t_Ready, and the register settings and NDEF memory must be restored afterward.
1	Enable RF	R/W	Global enable of RF interface. The RF interface should be disabled when writing to the NDEF memory. Enabling the RF interface triggers a basic check of the NDEF structure. If this check fails, the RF interface remains disabled and the NDEF Error interrupt flag is set. When the RF interface is enabled, writes using the serial interface (except to disable the RF interface) are discouraged to avoid any interference with RF communication. 0b = RF interface disabled 1b = RF interface enabled
2	Enable INT	R/W	Global Interrupt Output Enable 0b = Interrupt output disabled. The INTO pin is Hi-Z. 1b = Interrupt output enabled. The INTO pin signals any enabled interrupt according to the INTO High and INTO Drive bits.
3	INTO High	R/W	Interrupt Output pin INTO Configuration 0b = Interrupts are signaled with an active low 1b = Interrupts are signaled with an active high
4	INTO Drive	R/W	Interrupt Output pin INTO Configuration 0b = Pin is Hi-Z if there is no pending interrupt. Application provides an external pullup resistor if bit 3 (INTO Active High) = 0. Application provides an external pulldown resistor if bit 3 (INTO Active High) = 1. 1b = Pin is actively driven high or low if there is no pending interrupt. It is driven high if bit 3 (INTO Active High) = 0. It is driven low if bit 3 (INTO Active High) = 1.
5	BIP-8	R/W	Enables BIP-8 communication mode (bit interleaved parity). If BIP-8 is enabled, a separate running tally is kept of the parity (that is, the number of ones that occur) for every bit position in the bytes included in the BIP-8 calculation. The corresponding bit position of the BIP-8 byte is set to 1 if the parity is currently odd and is set to 0 if the parity is even – resulting in an overall even parity for each bit position including the BIP-8 byte. All communication when this bit is set must follow the conventions defined in the BIP-8 communication mode sections for I2C and SPI. 0b = BIP-8 communication mode disabled 1b = BIP-8 communication mode enabled
6	Standby Enable	R/W	Enables a low-power standby mode. The standby mode is entered if the RF interface is disabled, the communication watchdog is disabled, and no serial communication is ongoing. 0b = Standby mode disabled 1b = Standby mode enabled
7	Reserved	R/W
8-15	Reserved	R

5.7.2 Status Register

Table 5-11 Status Register

Addr:	15	14	13	12	11	10	9	8
0xFFFD	Reserved
Addr:	7	6	5	4	3	2	1	0
0xFFFC	Reserved					RF Busy	CRC Active	NDEF Ready

Table 5-12 Status Register Description

Bit	Field	Type	Description
0	Ready	R	0b = Device not ready to receive updates to the NDEF memory from the serial interface. 1b = Device ready. NDEF memory can be written by the serial interface.
1	CRC Active	R	0b = No CRC calculation ongoing 1b = CRC calculation ongoing
2	RF Busy	R	0b = No RF communication ongoing 1b = RF communication ongoing
3-15	Reserved	R

5.7.3 Interrupt Registers

The interrupt enable register (see Table 5-13 and Table 5-14) determines which interrupt events are signaled on the external output pin INTO. Setting any bit high in this register allows the corresponding event to trigger the interrupt signal. See Table 5-17 for a description of each interrupt.

All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO.

Table 5-13 Interrupt Enable Register

Addr:	15	14	13	12	11	10	9	8
0xFFFB	Reserved
Addr:	7	6	5	4	3	2	1	0
0xFFFA	Generic Error	Reserved	NDEF Error	BIP-8 Error Detected	CRC Calculation Completed	End of Write	End of Read	Reserved

Table 5-14 Interrupt Enable Register Description

Bit	Field	Type	Reset	Description
0-15	Interrupt Enables	R/W	0	Enable for the corresponding IRQ. All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO. 0b = IRQ disabled 1b = IRQ enabled

Bit

Field

Type

Reset

Description

0-15

Interrupt Enables

R/W

Enable for the corresponding IRQ. All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO.

0b = IRQ disabled

1b = IRQ enabled

The interrupt flag register (see Table 5-15 and Table 5-16) is used to report the status of any interrupts that are pending. Setting any bit high in this register acknowledges and clears the interrupt associated with the respective bit. See Table 5-17 for a description of each interrupt.

Table 5-15 Interrupt Flag Register

Addr:	15	14	13	12	11	10	9	8
0xFFF9	Reserved
Addr:	7	6	5	4	3	2	1	0
0xFFF8	Generic Error	Reserved	NDEF Error	BIP-8 Error Detected	CRC Calculation Completed	End of Write	End of Read	Reserved

Table 5-16 Interrupt Flag Register Description

Bit	Field	Type	Reset	Description
0-15	Interrupt Flags	R/W	0	Flag pending IRQ. Read Access: 0b = No pending IRQ. 1b = Pending IRQ. Write Access: 0b = No change. 1b = Clear pending IRQ flag.

Bit

Field

Type

Reset

Description

0-15

Interrupt Flags

R/W

Flag pending IRQ.

Read Access: 0b = No pending IRQ. 1b = Pending IRQ.

Write Access: 0b = No change. 1b = Clear pending IRQ flag.

Table 5-17 Interrupts

Bit	Field	Description
0	Reserved
1	End of Read	This IRQ occurs when the RF field is turned off by the reader after the reader has performed a read of the NDEF message.
2	End of Write	This IRQ occurs when the RF field is turned off by the reader after the reader has performed a write into the NDEF message.
3	CRC Calculation Completed	This IRQ occurs when a CRC calculation that is triggered by writing into the CRC registers is completed and the result can be read from the CRC result register (see Section 5.7.4).
4	BIP-8 Error Detected	This IRQ occurs when a BIP-8 error is detected (only if the BIP-8 communication mode is enabled).
5	NDEF Error	This IRQ occurs if an error is detected in the NDEF structure after an attempt to enable the RF interface.
6	Reserved
7	Generic Error	This IRQ occurs for any error that makes the device unreliable or non-operational.
8-15	Reserved

5.7.4 CRC Registers

Writing the CRC address and the CRC length registers initiates a 16-bit CRC calculation of the specified address range. The length is always assumed to be even (16-bit aligned). Writing the length register starts the CRC calculation.

During the CRC calculation, the CRC active bit is set (=1). When the calculation is complete, the "CRC completion" interrupt flag is set and the result of the CRC calculation can be read from the CRC result register. It is recommended to perform a CRC calculation only when the RF interface is disabled (RF Enable = 0).

Table 5-18 CRC Result Register

Addr:	15	14	13	12	11	10	9	8
0xFFF7	CRC CCITT Result (high byte)
Addr:	7	6	5	4	3	2	1	0
0xFFF6	CRC CCITT Result (low byte)

Table 5-19 CRC Result Register Description

Bit	Field	Type	Reset	Description
0-15	CRC-CCITT Result	R	0	CRC-CCITT Result

Table 5-20 CRC Length Register

Addr:	15	14	13	12	11	10	9	8
0xFFF5	CRC Length (high byte)
Addr:	7	6	5	4	3	2	1	0
0xFFF4	CRC Length (low byte)

Table 5-21 CRC Length Register Description

Bit	Field	Type	Reset	Description
0-15	CRC Length	RW	0	CRC Length - always assumed to be even (Bit 0 = 0). Writing into high byte starts CRC calculation.

Table 5-22 CRC Start Address Register

Addr:	15	14	13	12	11	10	9	8
0xFFF3	CRC Start Address (high byte)
Addr:	7	6	5	4	3	2	1	0
0xFFF2	CRC Start Address (low byte)

Table 5-23 CRC Start Address Register Description

Bit	Field	Type	Reset	Description
0-15	CRC Start Address	RW	0	CRC Start Address. Defines start address within NDEF memory. This address is always assumed to be even (bit 0 = 0).

The CRC is calculated based on the CCITT polynomial initialized with 0xFFFF.

CCITT polynomial: x¹⁶ + x¹² + x⁵ + 1

5.7.5 Communication Watchdog Register

When the communication watchdog is enabled, it expects a write or read access within a specified period; otherwise, the watchdog resets the device. If the BIP-8 communication mode is enabled, the transfer must be valid to be accepted as a watchdog reset.

Table 5-24 Communication Watchdog Register

Addr:	15	14	13	12	11	10	9	8
0xFFF1	Reserved
Addr:	7	6	5	4	3	2	1	0
0xFFF0	Reserved				Timeout Period Selection			Enable

Table 5-25 Communication Watchdog Register Description

Bit	Field	Type	Description
0	Enable	R/W	0b = Communication Watchdog disabled 1b = Communication Watchdog enabled
1	Timeout Period Selection	R/W	000b = 2 s ± 30%⁽¹⁾ 001b = 32 s ± 30%⁽¹⁾ 010b = 8.5 min ± 30%⁽¹⁾ 011b to 111b = Reserved
4-15	Reserved	R

Bit

Field

Type

Reset

Description

Enable

R/W

0b = Communication Watchdog disabled

1b = Communication Watchdog enabled

Timeout Period Selection

R/W

000b = 2 s ± 30%⁽¹⁾

001b = 32 s ± 30%⁽¹⁾

010b = 8.5 min ± 30%⁽¹⁾

011b to 111b = Reserved

4-15

Reserved

(1) This value is based on use of the integrated low-frequency oscillator with a frequency of 256 kHz ± 30%.

5.7.6 Version Registers

Provides version information about the implemented ROM code.

Table 5-26 Version Register

Addr:	15	14	13	12	11	10	9	8
0xFFEF	Software Version
Addr:	7	6	5	4	3	2	1	0
0xFFEE	Software Identification

Table 5-27 Version Register Description

Bit	Field	Type	Reset	Description
0-7	Software Identification	R		0x01: RF430CL330H Firmware
8-15	Software Version	R		Software version

5.8 NFC Type-4 Tag Functionality

This device is an ISO14443B-compliant transponder that operates according to the NFC Forum Tag Type-4 specification and supports the NFC Forum NDEF (NFC Data Exchange Format) requirements. Through the RF interface, the user can read and update the contents in the NDEF memory. The contents in the NDEF memory (stored in SRAM) are stored as long as power is maintained.

NOTE

This device does not have nonvolatile memory; therefore, the information stored in the NDEF memory is lost when power is removed.

This device does not support the peer-to-peer or reader/writer modes in the ISO18092/NFC Forum specification. All RF communication between an NFC forum device and this device is in the passive tag mode. The device responds by load modulation and is not considered an intentional radiator.

This device is intended to be used in applications where the primary reader/writer is for example an NFC-enabled cell phone. The device enables data transfer to and from an NFC phone by RF to the host application that is enabled with the dual interface device. In this case, the host application can be considered the destination device, and the cell phone or other type of mobile device is treated as the end-point device.

This device supports ISO14443-3, ISO14443-4, and NFC Forum commands as described in the following sections. A high-level overview of the ISO14443B and NFC commands and responses are shown in Figure 5-10.

106-kbps, 212-kbps, 424-kbps, and 848-kbps data rates are supported.

The device always answers ATTRIB commands from the PCD that request higher data rates. Note, this is not NFC-compliant, because for NFC-B the maximum data rate specified is 106 kbps. It is assumed that an NFC-compliant PCD would not request higher data rates thus no interoperability issues are expected.

Even though all data rates up to 848 kbps are supported, the device by default reports only the capability to support 106 kbps to the PCD. To change this behavior, use the sequence described in Section 5.8.3.

The ISO14443B command and response structure is detailed in ISO14443-3, ISO14443-4, and NFC Forum-TS-Digital Protocol. The applicable ISO7816-4 commands are detailed in NFC Forum-TS-Type-4-Tag_2.0.

RF430CL330H command_reponse_exchange_slas850.gif

Figure 5-10 Command and Response Exchange Flow

5.8.1 ISO14443-3 Commands

These commands use the character, frame format, and timing that are described in ISO14443-3, clause 7.1. The following commands are used to manage communication:

REQB and WUPB

The REQB and WUPB Commands sent by the PCD are used to probe the field for PICCs of Type B. In addition, WUPB is used to wake up PICCs that are in the HALT state. The number of slots N is included in the command as a parameter to optimize the anticollision algorithm for a given application.

Slot-MARKER

After a REQB or WUPB Command, the PCD may send up to (N-1) Slot-MARKER Commands to define the start of each timeslot. Slot-MARKER Commands can be sent after the end of an ATQB message received by the PCD to mark the start of the next slot or earlier if no ATQB is received (no need to wait until the end of a slot, if this slot is known to be empty).

ATTRIB

The ATTRIB Command sent by the PCD includes information required to select a single PICC. A PICC receiving an ATTRIB Command with its identifier becomes selected and assigned to a dedicated channel. After being selected, this PICC only responds to commands defined in ISO/IEC 14443-4 that include its unique CID.

HLTB

The HLTB Command is used to set a PICC in HALT state and stop responding to a REQB.

After answering to this command, the PICC ignores any commands except the WUPB.

5.8.2 NFC Tag Type 4 Commands

Select

Selection of applications or files

ReadBinary

Read data from file

UpdateBinary

Update (erase and write) data to file

5.8.3 Data Rate Settings

106-kbps, 212-kbps, 424-kbps, and 848-kbps data rates are supported by the device.

Even though all data rates up to 848 kbps are supported, the device by default reports only the capability to support 106 kbps to the PCD.

To change this behavior, follow these steps using the selected serial interface (I²C or SPI):

Read the version register.
Use the version register content to select one of the following sequences:
- If "Software Identification" = 01h and "Software Version" = 01h, follow the sequence in Table 5-28.
- If "Software Identification" = 01h and "Software Version" = 02h , follow the sequence in Table 5-29.
If you do not want to support all data rates up to 847 kbps, then change the Data Rate Capability byte (Data 0 of Step 3. Write Access) according to Table 5-30.
Perform the steps in the following tables.

Table 5-28 Data Rate Setting Sequence (Version = 0101h)

Access Type	Addr Bits 15 to 8	Addr Bits 7 to 0	Data 0	Data 1
1. Write Access	0xFF	0xE0	0x4E	0x00
2. Write Access	0xFF	0xFE	0x80	0x00
3. Write Access	0x2A	0xA4	0xC4⁽¹⁾	0x00
4. Write Access	0x28	0x14	0x00	0x00
5. Write Access	0xFF	0xE0	0x00	0x00

(1) Data Rate Capability according to Table 5-30. 0xC4: all data rates up to 847 kbps are supported.

Table 5-29 Data Rate Setting Sequence (Version = 0201h)

Access Type	Addr Bits 15 to 8	Addr Bits 7 to 0	Data 0	Data 1
1. Write Access	0xFF	0xE0	0x4E	0x00
2. Write Access	0xFF	0xFE	0x80	0x00
3. Write Access	0x2A	0x7C	0xC4⁽¹⁾	0x00
4. Write Access	0x28	0x14	0x00	0x00
5. Write Access	0xFF	0xE0	0x00	0x00

(1) Data Rate Capability according to Table 5-30. 0xC4: all data rates up to 847 kbps are supported.

Table 5-30 Data Rate Capability

Data Rata Capability Byte								Description
b7	b6	b5	b4	b3	b2	b1	b0	Description
0	0	0	0	0	0	0	0	PICC supports only 106-kbps in both directions (default).
1	x	x	x	0	x	x	x	Same data rate from PCD to PICC and from PICC to PCD compulsory
x	x	x	1	0	x	x	x	PICC to PCD, data rate supported is 212 kbps
x	x	1	x	0	x	x	x	PICC to PCD, data rate supported is 424 kbps
x	1	x	x	0	x	x	x	PICC to PCD, data rate supported is 847 kbps
x	x	x	x	0	x	x	1	PCD to PICC, data rate supported is 212 kbps
x	x	x	x	0	x	1	x	PCD to PICC, data rate supported is 424 kbps
x	x	x	x	0	1	x	x	PCD to PICC, data rate supported is 847 kbps

5.9 NDEF Memory

This device implements 3KB of SRAM memory that must be written with the NDEF Application data.

Table 5-31 shows the mandatory structure. The data can be accessed through the RF interface only after the NDEF memory is correctly initialized through the serial interface (I²C or SPI).

While writing into the NDEF memory, the RF interface must be disabled by clearing the Enable RF bit in the General Control register. After the NDEF memory is properly initialized, the RF interface can be enabled be setting the Enable RF bit in the General Control register to 1. When the RF interface is enabled, the basic NDEF structure is checked for correctness. If an error in the structure is detected, the NDEF Error IRQ is triggered, and the RF interface remains disabled (the Enable RF bit in the General Control register is cleared to 0).

If the NDEF application data must be modified through the serial interface after the RF interface is enabled, it is recommended to read the RF Busy bit in the Status register. If the RF interface is busy, defer disabling the RF interface until the RF transaction is completed (indicated by RF Busy bit = 0).

Figure 5-11 shows the recommended flow how to control the access to the NDEF memory.

The address range for the NDEF memory is 0x0000 to 0x0BFF.

Table 5-31 NDEF Application Data (Mandatory)

NDEF Application Selectable by Name = D2_7600_0085_0101h	Capability Container Selectable by File ID = E103h	2B - CCLen
		1B - Mapping version
		2B - MLe = 000F9h
		2B - MLc = 000F6h
		NDEF File Ctrl TLV	1B - Tag = 04h		The NDEF file control TLV is mandatory
			1B - Len = 06h
			6B - Val	2B - File Identifier
				2B - Max file size
				1B - Read access
				1B - Write access
	NDEF File Selectable by File ID = xxyyh	2B - Len			Mandatory NDEF file
		xB - Binary NDEF file content
		yB - Unused if Len < Max file size in File Ctrl TLV

Table 5-32 NDEF Application Data (Includes Proprietary Sections)

NDEF Application Selectable by Name = D2_7600_0085_0101h	Capability Container Selectable by File ID = E103h	2B - CCLen
		1B - Mapping version
		2B - MLe = 000F9h
		2B - MLc = 000F6h
		NDEF File Ctrl TLV	1B - Tag = 04h		The NDEF file control TLV is mandatory
			1B - Len = 06h
			6B - Val	2B - File Identifier
				2B - Max file size
				1B - Read access
				1B - Write access
		Proprietary File Ctrl TLV (1)	1B - Tag = 05h		Zero or more proprietary file control TLVs
			1B - Len = 06h
			6B - Val	2B - File Identifier
				2B - Max file size
				1B - Read access
				1B - Write access
		⋮
		Proprietary File Ctrl TLV (N)	1B - Tag = 05h
			1B - Len = 06h
			6B - Val	2B - File Identifier
				2B - Max file size
				1B - Read access
				1B - Write access
	NDEF File Selectable by File ID = xxyyh	2B - Len			Mandatory NDEF file
		xB - Binary NDEF file content
		yB - Unused if Len < Max file size in File Ctrl TLV
	Proprietary File (1) Selectable by File ID = xxyyh	2B - Len			Optional proprietary file
		xB - Binary proprietary file content
		yB - Unused if Len < Max file size in File Ctrl TLV
	⋮
	Proprietary File (N) Selectable by File ID = xxyyh	2B - Len			Optional proprietary file
		xB - Binary proprietary file content
		yB - Unused if Len < Max file size in File Ctrl TLV

Figure 5-11 Recommended NDEF Memory Flow

5.9.1 NDEF Error Check

With the RF interface is enabled, the basic NDEF structure is automatically checked for correctness. If any of the following conditions are true, the error check fails, an NDEF error IRQ is triggered, and the RF interface remains disabled.

CCLEN less than 0x000F or greater than 0xFFFE.
MLe value is less than 0xF. Note, for best performance the MLe value should be programmed to 0x00F9.
MLc is equal to zero. Note, for best performance the MLc value should be programmed to 0x00F6.
TLV tag does not equal 0x4.
TLV length does not equal 0x6.
File ID equals 0, or 0xE102, or 0xE103, or 0x3F00, or 0x3FFF, or 0xFFFF.
Max NDEF size is less than 0x5 or greater than 0xFFFE.
Read access is greater than 0 and less than 0x80.
Write Access is greater than 0 and less than 0x80.

Also the proprietary TLVs are checked. The check fails if any of the following conditions are true.

TLV tag does not equal 0x05.
TLV length does not equal 0x6.
File ID equals 0, or 0xE102, or 0xE103, or 0x3F00, or 0x3FFF, or 0xFFFF.
Max NDEF size is less than 0x5 or greater than 0xFFFE.
Read access is greater than 0 and less than 0x80.
Write Access is greater than 0 and less than 0x80.

5.10 Typical Usage Scenario

A typical usage scenario is as follows:

Write capability container and messages into the NDEF memory (starting from address 0) using the serial interface.
Enable interrupts (especially End of Read and End of Write).
Configure the interrupt pin INTO as needed and enable the RF interface.
Wait for interrupt signaled by INTO.
Disable RF interface (but keep INTO settings unchanged).
Read interrupt flag register to determine interrupt sources.
Clear interrupt flags. INTO returns to inactive state.
Read and modify NDEF memory as needed.
Enable RF interface again (keeping INTO settings unchanged) and continue with ⁽⁴⁾.

5.11 References

ISO/IEC 14443-2: 2001, Part 2: Radio frequency interface power and signal interface

ISO/IEC 14443-3: 2001, Part 3: Initialization and anticollision

ISO/IEC 14443-4: 2001, Part 4: Transmission protocols

ISO/IEC 18092, NFC Communication Interface and Protocol-1 (NFCIP-1)

ISO/IEC 21481, NFC Communication Interface Protocol-2 (NFCIP-2)

NDEF NFC Forum Spec, NFC Data Exchange Format Specification

6 器件和文档支持

6.1 器件支持

6.1.1 开发支持

6.1.1.1 入门和下一步

如需获得有助于您开发的 RF430 系列器件、工具及软件的更多信息，请访问 NFC/RFID 工具和软件页面。

动态近场通信 (NFC) 类型 4B 标志设计 (TIDM-DYNAMICNFCTAG) 列出了所需组件和布局考量因素，并提供了相关固件示例，用于指导在各项应用（例如蓝牙/Wi-Fi 配对，设备配置和诊断）中实现 NFC 或将 NFC 用作通用 NFC 接口。设计人员可利用提供的文档、硬件和示例代码，选择 MSP430™ MCU 或其它可选 MCU 快速实现 NFC功能。

6.1.2 器件和开发工具命名规则

为了指明产品开发周期所处的阶段，TI 为所有 RF430 MCU 器件和支持工具的产品型号分配了前缀。每个商业系列产品都具有以下三个前缀中的一个：RF、P 或 X（例如，RF430CL330H）。德州仪器 (TI) 建议为其支持的工具使用三个可用前缀指示符中的两个：RF 和 X。这些前缀代表了产品开发的发展阶段：即从工程原型设计（器件和工具中包含 X）直到完全合格的生产器件和工具（器件和工具中包含 RF）。

器件开发进化流程：

X - 试验器件不一定代表最终器件的电气技术规格

P - 最终的芯片模型符合器件的电气技术规格，但是未经完整的质量和可靠性验证

RF - 完全合格的生产器件

支持工具开发发展流程：

X - 还未经德州仪器 (TI) 完整内部质量测试的开发支持产品。

RF – 完全合格的开发支持产品

X 和 P 器件和 X 开发支持工具在供货时附带如下免责条款：

“开发的产品用于内部评估用途。”

RF 器件和 RF 开发支持工具已进行完全特性描述，并且器件的质量和可靠性已经完全论证。 TI 的标准保修证书适用。

预测显示原型器件（X 和 P）的故障率大于标准生产器件。由于它们的预计的最终使用故障率仍未定义，德州仪器 (TI) 建议不要将这些器件用于任何生产系统。只有合格的产品器件将被使用。

TI 器件的命名规则也包括一个带有器件系列名称的后缀。这个后缀包括封装类型（例如，RGE）和温度范围（例如，T）。Figure 6-1 提供了读取任一系列产品成员完整器件名称的图例。

Figure 6-1 器件命名规则

6.2 文档支持

以下文档对 RF430CL330H 器件进行了介绍。 www.ti.com.cn 网站上提供了这些文档的副本。

SLAZ540

RF430CL330H 器件勘误表。说明了 RF430CL330H 器件功能技术规格的已知例外情况。

SLOA187

通过近场通信 (NFC) 实现自动蓝牙 (R) 配对。这份合作完成的文档是 NFC 论坛之前发布的名为《NFC 论坛连接切换技术规范》的后续文档，之前发布的技术规范开始定义交互的结构和顺序，此交互使两个启用 NFC 的器件能够使用其他无线通信技术建立一个连接。这份应用报告解释了如何在一个嵌入式应用中使用 RF430CL330H 动态 NFC 应答机执行 NFC 论坛 / Bluetooth SIG 技术规范。

6.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参见 TI 的《使用条款》。

TI E2E™ 社区

TI 工程师间 (E2E) 社区。此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。

6.4 商标

MSP430, E2E are trademarks of Texas Instruments.

Bluetooth is a registered trademark of Bluetooth SIG, Inc.

Wi-Fi is a registered trademark of Wi-Fi Alliance.

All other trademarks are the property of their respective owners.

6.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符。

6.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

7 机械封装和可订购信息

7.1 封装信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

重要声明

德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改，并有权根据 JESD48最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售都遵循在订单确认时所提供的TI 销售条款与条件。

TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为有必要时才会使用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。

TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应用相关的风险，客户应提供充分的设计与操作安全措施。

TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予的直接或隐含权限作出任何保证或解释。TI所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服务的许可、授权、或认可。使用此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它知识产权方面的许可。

对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况下才允许进行复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。

在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件或服务的所有明示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。

客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品相关的所有法律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见故障的危险后果、监测故障及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因在此类安全关键应用中使用任何 TI 组件而对 TI及其代理造成的任何损失。

在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特有的可满足适用的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。

TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使用的特别协议。

只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同意，对并非指定面向军事或航空航天用途的 TI组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独力负责满足与此类使用相关的所有法律和法规要求。

TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949要求，TI不承担任何责任。

产品

数字音频: www.ti.com.cn/audio
放大器和线性器件: www.ti.com.cn/amplifiers
数据转换器: www.ti.com.cn/dataconverters
DLP® 产品: www.dlp.com
DSP - 数字信号处理器: www.ti.com.cn/dsp
时钟和计时器: www.ti.com.cn/clockandtimers
接口: www.ti.com.cn/interface
逻辑: www.ti.com.cn/logic
电源管理: www.ti.com.cn/power
微控制器 (MCU): www.ti.com.cn/microcontrollers
RFID 系统: www.ti.com.cn/rfidsys
OMAP应用处理器: www.ti.com/omap
无线连通性: www.ti.com.cn/wirelessconnectivity

应用

通信与电信: www.ti.com.cn/telecom
计算机及周边: www.ti.com.cn/computer
消费电子: www.ti.com/consumer-apps
能源: www.ti.com/energy
工业应用: www.ti.com.cn/industrial
医疗电子: www.ti.com.cn/medical
安防应用: www.ti.com.cn/security
汽车电子: www.ti.com.cn/automotive
视频和影像: www.ti.com.cn/video

德州仪器在线技术支持社区: www.deyisupport.com