ZHCS158C July   2012  – January 2017 ADS1299 , ADS1299-4 , ADS1299-6

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Switching Characteristics: Serial Interface
    8. 7.8 Typical Characteristics
  8. Parametric Measurement Information
    1. 8.1 Noise Measurements
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Functionality
        1. 9.3.1.1 Input Multiplexer
          1. 9.3.1.1.1 Device Noise Measurements
          2. 9.3.1.1.2 Test Signals (TestP and TestN)
          3. 9.3.1.1.3 Temperature Sensor (TempP, TempN)
          4. 9.3.1.1.4 Supply Measurements (MVDDP, MVDDN)
          5. 9.3.1.1.5 Lead-Off Excitation Signals (LoffP, LoffN)
          6. 9.3.1.1.6 Auxiliary Single-Ended Input
        2. 9.3.1.2 Analog Input
        3. 9.3.1.3 PGA Settings and Input Range
          1. 9.3.1.3.1 Input Common-Mode Range
          2. 9.3.1.3.2 Input Differential Dynamic Range
          3. 9.3.1.3.3 ADC ΔΣ Modulator
          4. 9.3.1.3.4 Reference
      2. 9.3.2 Digital Functionality
        1. 9.3.2.1 Digital Decimation Filter
          1. 9.3.2.1.1 Sinc Filter Stage (sinx / x)
        2. 9.3.2.2 Clock
        3. 9.3.2.3 GPIO
        4. 9.3.2.4 ECG and EEG Specific Features
          1. 9.3.2.4.1 Input Multiplexer (Rerouting the BIAS Drive Signal)
          2. 9.3.2.4.2 Input Multiplexer (Measuring the BIAS Drive Signal)
          3. 9.3.2.4.3 Lead-Off Detection
            1. 9.3.2.4.3.1 DC Lead-Off
            2. 9.3.2.4.3.2 AC Lead-Off (One Time or Periodic)
          4. 9.3.2.4.4 Bias Lead-Off
          5. 9.3.2.4.5 Bias Drive (DC Bias Circuit)
            1. 9.3.2.4.5.1 Bias Configuration with Multiple Devices
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start
        1. 9.4.1.1 Settling Time
      2. 9.4.2 Reset (RESET)
      3. 9.4.3 Power-Down (PWDN)
      4. 9.4.4 Data Retrieval
        1. 9.4.4.1 Data Ready (DRDY)
        2. 9.4.4.2 Reading Back Data
      5. 9.4.5 Continuous Conversion Mode
      6. 9.4.6 Single-Shot Mode
    5. 9.5 Programming
      1. 9.5.1 Data Format
      2. 9.5.2 SPI Interface
        1. 9.5.2.1 Chip Select (CS)
        2. 9.5.2.2 Serial Clock (SCLK)
        3. 9.5.2.3 Data Input (DIN)
        4. 9.5.2.4 Data Output (DOUT)
      3. 9.5.3 SPI Command Definitions
        1. 9.5.3.1  Sending Multi-Byte Commands
        2. 9.5.3.2  WAKEUP: Exit STANDBY Mode
        3. 9.5.3.3  STANDBY: Enter STANDBY Mode
        4. 9.5.3.4  RESET: Reset Registers to Default Values
        5. 9.5.3.5  START: Start Conversions
        6. 9.5.3.6  STOP: Stop Conversions
        7. 9.5.3.7  RDATAC: Read Data Continuous
        8. 9.5.3.8  SDATAC: Stop Read Data Continuous
        9. 9.5.3.9  RDATA: Read Data
        10. 9.5.3.10 RREG: Read From Register
        11. 9.5.3.11 WREG: Write to Register
    6. 9.6 Register Maps
      1. 9.6.1 User Register Description
        1. 9.6.1.1  ID: ID Control Register (address = 00h) (reset = xxh)
        2. 9.6.1.2  CONFIG1: Configuration Register 1 (address = 01h) (reset = 96h)
        3. 9.6.1.3  CONFIG2: Configuration Register 2 (address = 02h) (reset = C0h)
        4. 9.6.1.4  CONFIG3: Configuration Register 3 (address = 03h) (reset = 60h)
        5. 9.6.1.5  LOFF: Lead-Off Control Register (address = 04h) (reset = 00h)
        6. 9.6.1.6  CHnSET: Individual Channel Settings (n = 1 to 8) (address = 05h to 0Ch) (reset = 61h)
        7. 9.6.1.7  BIAS_SENSP: Bias Drive Positive Derivation Register (address = 0Dh) (reset = 00h)
        8. 9.6.1.8  BIAS_SENSN: Bias Drive Negative Derivation Register (address = 0Eh) (reset = 00h)
        9. 9.6.1.9  LOFF_SENSP: Positive Signal Lead-Off Detection Register (address = 0Fh) (reset = 00h)
        10. 9.6.1.10 LOFF_SENSN: Negative Signal Lead-Off Detection Register (address = 10h) (reset = 00h)
        11. 9.6.1.11 LOFF_FLIP: Lead-Off Flip Register (address = 11h) (reset = 00h)
        12. 9.6.1.12 LOFF_STATP: Lead-Off Positive Signal Status Register (address = 12h) (reset = 00h)
        13. 9.6.1.13 LOFF_STATN: Lead-Off Negative Signal Status Register (address = 13h) (reset = 00h)
        14. 9.6.1.14 GPIO: General-Purpose I/O Register (address = 14h) (reset = 0Fh)
        15. 9.6.1.15 MISC1: Miscellaneous 1 Register (address = 15h) (reset = 00h)
        16. 9.6.1.16 MISC2: Miscellaneous 2 (address = 16h) (reset = 00h)
        17. 9.6.1.17 CONFIG4: Configuration Register 4 (address = 17h) (reset = 00h)
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Unused Inputs and Outputs
      2. 10.1.2 Setting the Device for Basic Data Capture
        1. 10.1.2.1 Lead-Off
        2. 10.1.2.2 Bias Drive
      3. 10.1.3 Establishing the Input Common-Mode
      4. 10.1.4 Multiple Device Configuration
        1. 10.1.4.1 Cascaded Mode
        2. 10.1.4.2 Daisy-Chain Mode
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Sequencing
    2. 11.2 Connecting the Device to Unipolar (5 V and 3.3 V) Supplies
    3. 11.3 Connecting the Device to Bipolar (±2.5 V and 3.3 V) Supplies
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档 
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 Glossary
  14. 14机械、封装和可订购信息

Layout

Layout Guidelines

TI recommends employing best design practices when laying out a printed-circuit board (PCB) for both analog and digital components. This recommendation generally means that the layout separates analog components [such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of good component placement is shown in Figure 79. Although Figure 79 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog component.

ADS1299 ADS1299-4 ADS1299-6 ai_comp_plcmt_bas501.gif Figure 79. System Component Placement

The following outlines some basic recommendations for the layout of the ADS1299-x to get the best possible performance of the ADC. A good design can be ruined with a bad circuit layout.

  • Separate analog and digital signals. To start, partition the board into analog and digital sections where the layout permits. Route digital lines away from analog lines. This configuration prevents digital noise from coupling back into analog signals.
  • The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but is not necessary. Place digital signals over the digital plane, and analog signals over the analog plane. As a final step in the layout, the split between the analog and digital grounds must be connected together at the ADC.
  • Fill void areas on signal layers with ground fill.
  • Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground plane is cut or has other traces that block the current from flowing right next to the signal trace, then the current must find another path to return to the source and complete the circuit. If current is forced into a longer path, the chances that the signal radiates increases. Sensitive signals are more susceptible to EMI interference.
  • Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active device yields the best results.
  • Analog inputs with differential connections must have a capacitor placed differentially across the inputs. The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G (NPO), which have stable properties and low noise characteristics.

Layout Example

Figure 80 is an example layout of the ADS1299 requiring a minimum of two PCB layers. The example circuit is shown for either a single analog supply or a bipolar-supply connection. In this example, polygon pours are used as supply connections around the device. If a three- or four-layer PCB is used, the additional inner layers can be dedicated to route power traces. The PCB is partitioned with analog signals routed from the left, digital signals routed to the right, and power routed above and below the device.

ADS1299 ADS1299-4 ADS1299-6 recommended_layout_sbas499.gif Figure 80. ADS1299 Example Layout