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TPS40170 是一款功能齐全的同步 PWM 降压控制器,工作输入电压介于 4.5V 至 60V 之间,并针对高功率密度、高可靠性的直流/直流转换器应用进行了优化。该控制器通过输入电压前馈补偿实现电压模式控制,可在输入电压变化时即时响应。此器件具有 100kHz 至 600kHz 的可编程开关频率。
TPS40170 具有整套系统保护和监控特性,例如可编程欠压锁定 (UVLO)、通过检测低侧 FET 实现的可编程过流保护 (OCP)、通过检测高侧 FET 实现的可选短路保护 (SCP) 和热关断。通过 ENABLE 引脚,系统能够在低电流(典型值 1µA)模式下进行关断。控制器支持预偏置输出,提供开漏电源正常 (PGOOD) 信号,并具有闭环软启动、输出电压跟踪以及自适应死区时间控制功能。
TPS40170 可通过 1% 确保精度实现准确的输出电压调节。此外,该控制器还采用新型双向同步方案,即一个控制器作为主要控制器,其他下游控制器作为辅助控制器,辅助控制器可与主要控制器同相或 180° 异相同步。辅助控制器可在自由运行开关频率的 ±30% 范围内与外部时钟同步。
新款产品(LM5145 和 LM5146)具有 BOM 成本低、效率高、设计尺寸小等诸多特性。
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 9 | — | Analog signal ground. This pin must be electrically connected to power ground PGND externally. |
BOOT | 18 | O | Boot capacitor node for high-side FET gate driver. The boot capacitor is connected from this pin to SW. |
COMP | 8 | O | Output of the internal error amplifier. The feedback loop compensation network is connected from this pin to the FB pin. |
ENABLE | 1 | I | This pin must be high for the device to be enabled. If this pin is pulled low, the device is put in a low-power consumption shutdown mode. |
FB | 7 | I | Negative input to the error amplifier. The output voltage is fed back to this pin through a resistor divider network. |
HDRV | 17 | O | Gate driver output for the high-side FET. |
ILIM | 12 | I | A resistor from this pin to PGND sets the overcurrent limit. This pin provides source current used for overcurrent protection threshold setting. |
LDRV | 14 | O | Gate driver output for the low-side FET. Also, a resistor from this pin to PGND sets the multiplier factor to determine short-circuit current limit. If no resistor is present the multiplier defaults to 7 times the ILIM pin voltage. |
M/S | 3 | I | Primary or secondary mode selector pin for frequency synchronization. This pin must be tied to VIN for primary mode. In the secondary mode this pin must be tied to AGND or left floating. If the pin is tied to AGND, the device synchronizes with a 180° phase shift. If the pin is left floating, the device synchronizes with a 0° phase shift. |
PGND | 13 | — | Power ground. This pin must externally connect to the AGND at a single point. |
PGOOD | 11 | O | Power good indicator. This pin is an open-drain output pin and a 10 kΩ pull-up resistor is recommended to be connected between this pin and VDD. |
RT | 4 | I | A resistor from this pin to AGND sets the oscillator frequency. Even if operating in secondary mode, it is required to have a resistor at this pin to set the free running switching frequency. |
SS | 5 | I | Soft-start. A capacitor must be connected at this pin to AGND. The capacitor value sets the soft-start time. |
SW | 16 | I | This pin must connect to the switching node of the synchronous buck converter. The high-side and low-side FET current sensing are also done from this node. |
SYNC | 2 | I/O | Synchronization. This is a bi-directional pin used for frequency synchronization. In the primary mode, it is the SYNC output pin. In the secondary mode, it is a SYNC input pin. If unused, this pin can be left open. |
TRK | 6 | I | Tracking. External signal at this pin is used for output voltage tracking. This pin goes directly to the internal error amplifier as a positive reference. The lesser of the voltages between VTRK and the internal 600 mV reference sets the output voltage. If not used, this pin must be pulled up to VDD. |
UVLO | 20 | I | Undervoltage lockout. A resistor divider on this pin from VIN to AGND can be used to set the UVLO threshold. |
VBP | 15 | O | 8 V regulated output for gate driver. A ceramic capacitor with a value from 1 µF to 10 µF must be connected from this pin to PGND and placed close to this pin. |
VDD | 10 | O | 3.3 V regulated output. A ceramic by-pass capacitor with a value from 0.1 µF to 1 µF must be connected from this pin to AGND and placed close to this pin. |
VIN | 19 | I | Input voltage for the controller which is also the input voltage for the DC/DC converter. A ceramic by-pass capacitor with a value from 0.1 µF to 1 µF must be connected from this pin to PGND and placed close to this pin. |
over operating free-air temperature range (unless otherwise noted)
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN | –0.3 | 62 | V |
M/S | –0.3 | VIN | ||
UVLO | –0.3 | 16 | ||
SW | –5 | VVIN | ||
SW (for duration less than 200 ns) | –10 | VVIN | ||
BOOT | VSW + 8.8 | |||
Output voltage | HDRV | VSW | BOOT | V |
BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW) | –0.3 | 8.8 | ||
VBP, LDRV, COMP, RT, ENABLE, PGOOD, SYNC | –0.3 | 8.8 | ||
VDD, FB, TRK, SS, ILIM | –0.3 | 3.6 | ||
AGND-PGND, PGND-AGND | 200 | 200 | mV | |
PowerPAD to AGND (must be electrically connected external to device) | 0 | |||
Lead Temperature | 260 | °C | ||
Operating junction temperature | TJ | –40 | 125 | °C |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature | –55 | 150 | °C | |
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | 2000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | 1000 |
over operating free-air temperature range (unless otherwise noted)
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN | Input voltage | 4.5 | 60 | V |
TJ | Operating junction temperature range | -40 | 125 | °C |
THERMAL METRIC(1) | TPS40170 | UNIT | |
---|---|---|---|
RGY | |||
20 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 35.0 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 36.7 | |
RθJB | Junction-to-board thermal resistance | 12.6 | |
ψJT | Junction-to-top characterization parameter | 0.4 | |
ψJB | Junction-to-board characterization parameter | 12.7 | |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | 3.1 |
Unless otherwise stated, these specifications apply for –40ºC ≤ TJ ≤ 125ºC, VVIN=12 V
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT SUPPLY | ||||||
VVIN | Input voltage range | 4.5 | 60 | V | ||
ISD | Shutdown current | VENABLE < 100 mV | 1 | 2.5 | µA | |
IQ | Operating current, drivers not switching | VENABLE ≥ 2 V, fSW = 300 kHz | 4.5 | mA | ||
ENABLE | ||||||
VDIS | ENABLE pin voltage to disable the device | 100 | mV | |||
VEN | ENABLE pin voltage to enable the device | 600 | ||||
IENABLE | ENABLE pin source current | 300 | nA | |||
8-V AND 3.3-V REGULATORS | ||||||
VBP | 8 V regulator output voltage | VENABLE ≥ 2 V, 8.2 V < VIN ≤ 60 V, 0 mA < IIN < 20 mA |
7.8 | 8.0 | 8.3 | V |
VDO | 8 V regulator dropout voltage, VIN-BP |
4.5 < VIN ≤ 8.2 V, VEN ≥ 2.0 V, IIN = 10 mA |
110 | 200 | mV | |
VVDD | 3.3 V regulator output voltage | VENABLE ≥ 2 V, 4.5 V < VIN ≤ 60 V, 0 mA < IIN < 5 mA |
3.22 | 3.30 | 3.42 | V |
FIXED AND PROGRAMMABLE UVLO | ||||||
VUVLO | Programmable UVLO ON voltage (at UVLO pin) | VENABLE ≥ 2 V | 878 | 900 | 919 | mV |
IUVLO | Hysteresis current out of UVLO pin | VENABLE ≥ 2 V , UVLO pin > VUVLO | 4.06 | 5.00 | 6.20 | µA |
VBP(ON) | VBP turn-on voltage | VENABLE ≥ 2 V, UVLO pin > VUVLO | 3.85 | 4.40 | V | |
VBP(OFF) | VBP turn-off voltage | 3.60 | 4.05 | |||
VBP(HYS) | VBP UVLO Hysteresis voltage | 180 | 400 | mV | ||
REFERENCE | ||||||
VREF | Reference voltage (+ input of the error amplifier) | TJ = 25°C, 4.5 V < VIN ≤ 60 V | 594 | 600 | 606 | mV |
–40°C ≤ TJ ≤ 125ºC, 4.5 V < VIN ≤ 60 V | 591 | 600 | 609 | |||
OSCILLATOR | ||||||
fSW | Switching frequency | Range (typical) | 100 | 600 | kHz | |
RRT = 100 kΩ, 4.5 V <VIN ≤ 60 V | 90 | 100 | 110 | |||
RRT = 31.6 kΩ, 4.5 V <VIN ≤ 60 V | 270 | 300 | 330 | |||
RRT = 14.3 kΩ, 4.5 V <VIN ≤ 60 V | 540 | 600 | 660 | |||
VVALLEY | Valley voltage | 0.7 | 1 | 1.2 | V | |
KPWM(1) | PWM Gain (VIN / VRAMP) | 4.5 V < VIN ≤ 60 V | 14 | 15 | 16 | V/V |
PWM AND DUTY CYCLE | ||||||
tON(min)(1) | Minimum controlled pulse | VIN = 4.5 V, fSW = 300 kHz | 100 | 150 | ns | |
VIN = 12 V, fSW = 300 kHz | 75 | 100 | ||||
VIN = 60 V, fSW = 300 kHz | 50 | 80 | ||||
tOFF(max)(1) | Minimum OFF time | VIN = 12 V, fSW = 300 kHz | 170 | 250 | ||
DMAX(1) | Maximum duty cycle | fSW = 100 kHz, 4.5 V < VIN ≤ 60 V | 95% | |||
FSW = 300 kHz, 4.5 V < VIN ≤ 60 V | 91% | |||||
fSW = 600 kHz, 4.5 V < VIN ≤ 60 V | 82% | |||||
ERROR AMPLIFIER | ||||||
GBWP(1) | Gain bandwidth product | 7 | 10 | 13 | MHz | |
AOL(1) | Open-loop gain | 80 | 90 | 95 | dB | |
IIB | Input bias current | 100 | nA | |||
IEAOP | Output source current | VFB = 0 V | 2 | mA | ||
IEAOM | Output sink current | VFB = 1 V | 2 | |||
PROGRAMMABLE SOFT-START | ||||||
ISS(source,start) | Soft-start source current at VSS < 0.5 V | VSS = 0.25 V | 42 | 52 | 62 | µA |
ISS(source,normal) | Soft-start source current at VSS > 0.5 V | VSS = 1.5 V | 9.3 | 11.6 | 13.9 | |
ISS(sink) | Soft-start sink current | VSS = 1.5 V | 0.77 | 1.05 | 1.33 | |
VSS(fltH) | SS pin HIGH voltage during fault (OC or thermal) reset timing | 2.38 | 2.50 | 2.61 | V | |
VSS(fltL) | SS pin LOW voltage during fault (OC or thermal) reset timing | 235 | 300 | 375 | mV | |
VSS(steady_state) | SS pin voltage during steady-state | 3.25 | 3.30 | 3.50 | V | |
VSS(offst) | Initial offset voltage from SS pin to error amplifier input | 525 | 650 | 775 | mV | |
TRACKING | ||||||
VTRK(ctrl)(1) | Range of TRK which overrides VREF | 4.5 V < VIN ≤ 60 V | 0 | 600 | mV | |
SYNCHRONIZATION (PRIMARY/SECONDARY) | ||||||
VMSTR | M/S pin voltage in primary mode | 3.9 | VIN | V | ||
VSLV(0) | M/S pin voltage in secondary 0 deg mode | 1.25 | 1.75 | |||
VSLV(180) | M/S pin voltage in secondary 180 deg mode | 0 | 0.75 | |||
ISYNC(in) | SYNC pin pull-down current | M/S configured as secondary- 0 degrees or secondary-180 degrees |
8 | 11 | 14 | µA |
VSYNC(in_high) | SYNC pin input high-voltage level | 2 | V | |||
VSYNC(in_low) | SYNC pin input low-voltage level | 0.8 | ||||
tSYNC(high_min) | Minimum SYNC high pulse-width | 40 | 50 | ns | ||
tSYNC(low_min) | Minimum SYNC low pulse-width | 40 | 50 | |||
GATE DRIVERS | ||||||
RHDHI | High-side driver pull-up resistance | CLOAD = 2.2 nF, IDRV = 300 mA | 1.37 | 2.64 | 3.50 | Ω |
RHDLO | High-side driver pull-down resistance | 1.08 | 2.40 | 3.35 | ||
RLDHI | Low-side driver pull-up resistance | 1.37 | 2.40 | 3.20 | ||
RLDLO | Low-side driver pull-down resistance | 0.44 | 1.10 | 1.70 | ||
tNON-OVERLAP1 | Time delay between HDRV fall and LDRV rise | CLOAD = 2.2 nF, VHDRV = 2 V, VLDRV = 2 V |
50 | ns | ||
tNON-OVERLAP2 | Time delay between HDRV rise and LDRV fall | 60 | ||||
OVERCURRENT PROTECTION (LOW-SIDE MOSFET SENSING) | ||||||
IILIM | ILIM pin source current | 4.5 V < VIN < 60 V, TJ = 25°C | 9.00 | 9.75 | 10.45 | µA |
IILIM,(ss) | ILIM pin source current during Soft-start | 15 | ||||
IILIM, Tc(1) | Temperature coefficient of ILIM current | 4.5 V < VIN < 60 V | 1400 | ppm | ||
VILIM(1) | ILIM pin voltage operating range | 4.5 V < VIN < 60 V | 50 | 300 | mV | |
OCPTH | Overcurrent protection threshold (Voltage across low-side FET for detecting overcurrent) | RILIM = 10 kΩ, IILIM = 10 µA (VILIM = 100 mV) |
–110 | –100 | –84 | |
SHORT CIRCUIT PROTECTION HIGH-SIDE MOSFET SENSING) | ||||||
VLDRV(max) | LDRV pin maximum voltage during calibration | RLDRV = open | 300 | 360 | mV | |
AOC3 | Multiplier factor to set the SCP based on OCP level setting at the ILIM pin | RLDRV = 10 kΩ | 2.75 | 3.20 | 3.60 | V/V |
AOC7 | RLDRV = open | 6.40 | 7.25 | 7.91 | ||
AOC15 | RLDRV = 20 kΩ | 13.9 | 16.4 | 18.0 | ||
THERMAL SHUTDOWN | ||||||
TSD,set(1) | Thermal shutdown set threshold | 4.5 V < VIN < 60 V | 155 | 165 | 175 | °C |
TSD,reset(1) | Thermal shutdown reset threshold | 125 | 135 | 145 | ||
Thyst(1) | Thermal shutdown hysteresis | 30 | ||||
POWERGOOD | ||||||
VOV | FB pin voltage upper limit for power good | 4.5 V < VIN < 60 V | 627 | 647 | 670 | mV |
VUV | FB pin voltage lower limit for power good | 527 | 552 | 570 | ||
VPG,HYST | Power good hysteresis voltage at FB pin | 8.5 | 20.0 | 32.0 | ||
VPG(out) | PGOOD pin voltage when FB pin voltage > VOV or < VUV, IPGD=2 mA | 100 | ||||
VPG(np) | PGOOD pin voltage when device power is removed | VIN is open, 10 kΩ to VEXT = 5 V | 1 | 1.5 | V | |
BOOT DIODE | ||||||
VDFWD | Bootstrap diode forward voltage | I = 20 mA | 0.5 | 0.7 | 0.9 | V |
RBOOT-SW | Discharge resistor from BOOT to SW | 1 | MΩ |
The TPS40170 is a synchronous, PWM buck controller that accepts a wide range of input voltage from 4.5 V to 60 V and features voltage-mode control with input-voltage, feed-forward compensation. The switching frequency is programmable from 100 kHz to 600 kHz.
The TPS40170 has a complete set of system protections such as programmable undervoltage lockout (UVLO), programmable overcurrent protection (OCP), selectable short-circuit protection (SCP), and thermal shutdown. The ENABLE pin allows for system shutdown in a low-current (1-µA typical) mode. The controller supports pre-biased outputs, provides an open-drain PGOOD signal, and has closed loop programmable soft-start, output voltage tracking, and adaptive dead time control.
The TPS40170 provides accurate output voltage regulation through 1% specified accuracy.
Additionally, the controller implements a novel scheme of bidirectional synchronization with one controller acting as the primary other downstream controllers acting as secondaries, synchronized to the primary in-phase or 180° out-of-phase. Secondary controllers can be synchronized to an external clock within ±30% of the internal switching frequency.
The TPS40170 has two internal low-drop-out (LDO) linear regulators. One has a nominal output voltage of VVBP and is present at the VBP pin. This is the voltage that is mainly used for the gate-driver output. The other linear regulator has an output voltage of VVDD and is present at the VDD pin. This voltage can be used in external low-current logic circuitry. The maximum allowable current drawn from the VDD pin must not exceed 5 mA.
The TPS40170 has a dedicated device enable pin (ENABLE). This simplifies user level interface design because no multiplexed functions exist. If the ENABLE pin of the TPS40170 is higher than VEN, then the LDO regulators are enabled. To ensure that the LDO regulators are disabled, the ENABLE pin must be pulled below VDIS. By pulling the ENABLE pin below VDIS, the device is completely disabled and the current consumption is very low (nominally, 1 µA). Both LDO regulators are actively discharged when the ENABLE pin is pulled below VDIS. A functionally equivalent circuit to the enable circuitry on the TPS40170 is shown in Figure 6-1.
The ENABLE pin must not be allowed to float. If the ENABLE function is not needed for the design, then it is suggested that the ENABLE pin be pulled up to VIN by a high value resistor ensuring that the current into the ENABLE pin does not exceed 10 µA. If it is not possible to meet this clamp current requirement, then it is suggested that a resistor divider from VIN to GND be used to connect to ENABLE pin. The resistor divider must be such that the ENABLE pin must be higher than VEN and lower than 8 V.
To avoid potential erroneous behavior of the enable function, the ENABLE signal applied must have a minimum slew rate of 20 V/s.
The TPS40170 has both fixed and programmable input undervoltage lockout (UVLO). In order for the device to turn ON, all of the following conditions must be met:
In order for the device to turn OFF, any one of the following conditions must be met:
Programming the input UVLO can be accomplished using the UVLO pin. A resistor divider from the input voltage (VIN pin) to GND sets the UVLO level. After the input voltage reaches a value that meets the VUVLO level at the UVLO pin, then a small hysteresis current, IUVLO at the UVLO pin is switched in. The programmable UVLO function is shown in Figure 6-2.
Components R1 and R2 represent external resistors for programming UVLO and hysteresis and can be calculated in Equation 1 and Equation 2 respectively.
where
If the UVLO pin is connected to a voltage greater than 0.9 V, the programmable UVLO is disabled and the device defaults to an internal UVLO (VBP(on) and VBP(off)). For example, the UVLO pin can be connected to VDD or the VBP pin to disable the programmable UVLO function.
A 1 nF ceramic by-pass capacitor must be connected between the UVLO pin and GND.
TPS40170 implements an oscillator with input-voltage feed-forward compensation that enables instant response to input voltage changes. Figure 6-3 shows the oscillator timing diagram for the TPS40170. The resistor from the RT pin to GND sets the free running oscillator frequency. The voltage VRT on the RT pin is made proportional to the input voltage (see Equation 3).
where
The resistor at the RT pin sets the current in the RT pin. The proportional current charges an internal 100-pF oscillator capacitor. The ramp voltage on this capacitor is compared with the RT pin voltage, VRT. After the ramp voltage reaches VRT, the oscillator capacitor is discharged. The ramp that is generated by the oscillator (which is proportional to the input voltage) acts as voltage feed-forward ramp to be used in the PWM comparator.
The time between the start of the discharging oscillator capacitor and the start of the next charging cycle is fixed at 170 ns (typical). During the fixed discharge time, the PWM output is maintained as OFF. This is the minimum OFF-time of the PWM output.
where
The switching frequency can be adjusted between 100 kHz and 600 kHz. The maximum switching frequency before skipping pulses is determined by the input voltage, output voltage, FET resistances, DCR of the inductor, and the minimum on time of the TPS40170. Use Equation 5 to determine the maximum switching frequency. For further details, please see analog design journal, Understanding output voltage limitations of DC/DC buck converters.
where
The TPS40170 has the capability to set a two-level overcurrent protection. The first level of overcurrent protection (OCP) is the normal overload setting based on low-side MOSFET voltage sensing. The second level of protection is the heavy overload setting such as short-circuit based on the high-side MOSFET voltage sensing. This protection takes effect immediately. The second level is termed short-circuit protection (SCP).
The OCP level is set by the ILIM pin voltage. A current (IILIM) is sourced into the ILIM pin from which a resistor RILIM is connected to GND. Resistor RILIM sets the first level of overcurrent limit. The OCP is based on the low-side FET voltage at the switch-node (SW pin) when the LDRV is ON after a blanking time, which is the product of inductor current and low-side FET turn-on resistance RDS(on). The voltage is inverted and compared to ILIM pin voltage. If it is greater than the ILIM pin voltage, then a 3-bit counter inside the device increments the fault-count by 1 at the start of the next switching cycle. Alternatively, if it is less than the ILIM pin voltage, then the counter inside the device decrements the fault-count by 1. When the fault-count reaches 7, an overcurrent fault (OC_FAULT) is declared and both the HDRV and LDRV are turned OFF. The resistor RILIM can be calculated by the following Equation 6.
The SCP level is set by a multiple of the ILIM pin voltage. The multiplier has three discrete values, 3, 7 or 15 times, which can be selected by respectively choosing a 10-kΩ, open circuit, or 20 kΩ resistor from LDRV pin to GND. This multiplier AOC information is translated during the tCAL time, which starts after the enable and UVLO conditions are met.
The SCP is based on sensing the high-side FET voltage drop from VVIN to VSW when the HDRV is ON after a blanking time, which is product of inductor current and high-side FET turn-on resistance RDS(on). The voltage is compared to the product of multiplier and the ILIM pin voltage. If it exceeds the product, then the fault-count is immediately set to 7 and the OC_FAULT is declared. The HDRV is terminated immediately without waiting for the duty cycle to end. When an OC_FAULT is declared, both the HDRV and LDRV are turned OFF. The appropriate multiplier (A), can be selected using Equation 7.
Figure 6-4 shows the functional block of the two-level overcurrent protection.
Both OCP and SCP are based on low-side and high-side MOSFET voltage sensing at the SW node. Excessive ringing on the SW node can have negative impact on the accuracy of OCP and SCP. Adding an RC snubber from the SW node to GND helps minimize the potential impact.