ZHCABL3 February   2022 DAC43204 , DAC53004 , DAC53204 , DAC53204W , DAC63004 , DAC63204

 

  1.   设计目标
  2.   设计说明
  3.   设计注意事项
  4.   设计仿真
    1.     瞬态仿真结果
    2.     直流传输仿真结果
  5.   寄存器设置
  6.   伪代码示例
  7.   设计中采用的器件
  8.   设计参考资料

伪代码示例

下面所示为将初始寄存器值编程到 DAC53204 的 NVM 的伪代码序列。此处给出的值基于在设计注意事项中所做的设计选择。

电压输出配置的伪代码示例

1：  //SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>  
2:  //Configure GPI for margin high/low trigger
3:  WRITE GPIO-CONFIG(0x24), 0x00, 0x35 
4:  //With 16-bit left alignment 0x3FF becomes 0xFFC0
5:  WRITE DAC-0-MARGIN-HIGH(0x01), 0xFF, 0xC0
6:  //With 16-bit left alignment 0x333 becomes 0xCCC0
7:  WRITE DAC-0-MARGIN-LOW(0x02), 0xCC, 0xC0
8:  //Set the CODE-SETP to 1 LSB and SLEW-RATE to 4 µs/step
9:  WRITE DAC-0-FUNC-CONFIG(0x06), 0x00, 0x01
10: //Power-up voltage output on channel 0, internal reference disabled
11: WRITE GENERAL_CONFIG(0x1F), 0x0F, 0xF9 
12: //Save settings to NVM
13: WRITE COMMON-TRIGGER(0x20), 0x00, 0x02

电流输出配置的伪代码示例

1：  //SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>  
2:  //Configure GPI for deep-sleep trigger and enable deep-sleep function
3:  WRITE GPIO-CONFIG(0x24), 0x00, 0x35 
4:  //With 16-bit left alignment 0x80 becomes 0x8000
5:  WRITE DAC-0-MARGIN-HIGH(0x01), 0x80, 0x00
6:  //Write DAC0 margin low code
7:  WRITE DAC-0-MARGIN-LOW(0x02), 0x00, 0x00
8:  //Set the CODE-SETP to 1 LSB and SLEW-RATE to 4 µs/step
9:  WRITE DAC-0-FUNC-CONFIG(0x06), 0x00, 0x01
10: //Power-up current output on channel 0, internal reference disabled
11: WRITE GENERAL_CONFIG(0x1F), 0x0F, 0xFE 
12: //Save settings to NVM
13: WRITE COMMON-TRIGGER(0x20), 0x00, 0x02