TIDT256A March   2022  – March 2022

 

  1.   Description
  2.   Features
  3.   Applications
  4. 1Test Prerequisites
    1. 1.1 LM5156-Q1
      1. 1.1.1 Loading LM5156-Q1
      2. 1.1.2 LM5156-Q1 SEPIC Bode Loop Testing
    2. 1.2 Loading UCC14240-Q1
    3. 1.3 UCC5870-Q1 and UCC5870-Q1 EVM GUI
    4. 1.4 Voltage and Current Requirements
    5. 1.5 Required Equipment
    6. 1.6 Considerations
    7. 1.7 Dimensions
  5. 2Testing and Results
    1. 2.1 SEPIC Efficiency Graphs
    2. 2.2 SEPIC Efficiency Data
    3. 2.3 SEPIC Bode Plots
    4. 2.4 Thermal Images
  6. 3Waveforms
    1. 3.1 SEPIC Switching
    2. 3.2 SEPIC Output Voltage Ripple
    3. 3.3 SEPIC Load Transients
    4. 3.4 SEPIC Start-Up Sequence
    5. 3.5 Isolated Bias Supply Start Up and Shutdown
    6. 3.6 Isolated Gate Drive

1.1.2 LM5156-Q1 SEPIC Bode Loop Testing

Complete the following for bode loop testing:

  1. Cut the connection from R15 to TP3 (24 V). This cut is bridged with 49.9 Ω and is called R100.
  2. On the PCB, cut the TP8 connection to U2–13. R10 (power good pullup) is not populated.
  3. Populate TP8 with a green through-hole test point (Keystone 5116) and tie to a connection between R100 and R115. TP8 becomes a signal injection point for the bode plot.
  4. Use a network analyzer such as the Bode 100 from Omricon Lab with the following:
    • V1 measured between injection point TP8 and ground TP10
    • V2 measured between VOUT TP3 and ground
    • Actual signal injection between TP8 and TP3