SWRZ148A December   2024  – December 2025 IWRL6432W

 

  1.   1
  2.   ABSTRACT
  3. 1Introduction
  4. 2Device Nomenclature
  5. 3Device Markings
  6. 4Usage Notes
    1. 4.1 Power up sequence in power optimized topology
    2. 4.2 Meeting data sheet spec for 1.2V Digital LDO output path in BOM optimized topology
  7. 5Advisory to Silicon Variant / Revision Map
  8. 6Known Design Exceptions to Functional Specifications
    1. 6.1  ANA #51
    2. 6.2  ANA #57
    3. 6.3  DIG #1
    4. 6.4  DIG #3
    5. 6.5  DIG #4
    6. 6.6  DIG #5
    7. 6.7  DIG #6
    8. 6.8  DIG #8
    9. 6.9  DIG #9
    10. 6.10 DIG #10
    11. 6.11 DIG #14
    12. 6.12 DIG #15
    13. 6.13 DIG #16
  9. 7Trademarks
  10.   Revision History

5 Advisory to Silicon Variant / Revision Map

Table 5-1 Advisory to Silicon Variant / Revision Map
Advisory Number Advisory Title IWRL6432W
ES2.1
Analog / Millimeter Wave

ANA #51

Continuous Wave Streaming CZ mode: Sudden jump in RX output codes every 20.97152msec

 x
ANA#57 SNR degradation at 60GHz in the presence of strong near range reflector x
Digital Subsystem
DIG #1 ePWM: Glitch during Chopper mode of operation x
DIG #3 Limited UART baud rates x
DIG #4 RS232 AutoBaud Rate feature doesn't support trimmed ROCSC variation. x
DIG #5 Internal Bus access to SPI for data transfer not supported when SPI smart-idle mode is enabled. x
DIG #6 CRC: CRC 8-bit data width and CRC8-SAE-J1850 and CRC8-H2F possible use in CAN module is not supported x
DIG #8 Shared RAM clock gating default values x
DIG #9 TOP_IO_MUX register space not accessible from RS232 for debug purposes. x
DIG #10 Incorrect behavior of frame stop API x
DIG #14 Corrupted Data Store for Partial Write in Shared Memory x
DIG #15 Boot failure, if metaimage is multiple of 2K x
DIG #16 Boot failure for images less than size 8k over SPI x