SWRZ131A september   2022  – june 2023 CC1354R10

ADVANCE INFORMATION  

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Advisories Matrix
  5. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  6. 3Advisories
    1.     Radio_01
    2. 3.1 Radio_05
    3.     Power_03
    4.     PKA_01
    5.     PKA_02
    6.     I2C_01
    7.     I2S_01
    8.     CPU_Sys_01
    9.     Sys_01
    10. 3.2 Sys_06
    11.     SYSCTRL_01
    12.     IOC_01
    13.     ADC_02
  7. 4Revision History

SYSCTRL_01

Resets Occurring in a Specific 2 MHz Period During Initial Power Up are Incorrectly Reported

Revisions Affected:

Revision B

Details:

If a reset occurs in a specific 2 MHz period during initial power-up (boot), the reset source in AON_PMCTL.RESETCTL.RESET_SRC is reported as PWR_ON regardless of the reset source. This means that there is a window of 0.5 μs during boot where a reset can be incorrectly reported.

Workaround:

None