SWRZ119A February   2022  – October 2026 CC1311R3

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Advisories Matrix
  5. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  6. 3Advisories
    1.     Radio_01
    2.     Power_03
    3.     I2C_01
    4.     I2S_01
    5.     CPU_01
    6.     CPU_02
    7.     CPU_Sys_01
    8.     Sys_01
    9.     Sys_05
    10.     SYSCTRL_01
    11.     IOC_01
    12.     ADC_01
    13.     ADC_02
    14.     ADC_03
  7. 4Revision History

I2C_01

I2C module master status bit is set late

Revisions Affected:

Revision C and earlier

Details:

The I2C.MSTAT[0] bit is not set immediately after writing to the I2C.MCTRL register. This can lead an I2C master to believe it is no longer busy and continuing to write data.

Workaround:

Add four NOPs between writing to the MCTRL register and polling the MSTAT register.

The workaround is implemented in the TI-provided I2C Master driver (I2CCC26XX.c) and in the I2C driver Library APIs (driverlib/i2c.c).

The workaround is available in all Software Development Kit (SDK) versions.