SPRZ450A February   2018  – October 2019 DRA74P , DRA75P , DRA76P , DRA77P

 

  1. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  2. 2Silicon Advisories
    1.     Revisions SR 1.0 - Advisories List
    2.     i202
    3.     i378
    4.     i631
    5.     i694
    6.     i698
    7.     i699
    8.     i709
    9.     i727
    10.     i729
    11.     i734
    12.     i767
    13.     i782
    14.     i783
    15.     i802
    16.     i803
    17.     i807
    18.     i808
    19.     i809
    20.     i810
    21.     i813
    22.     i814
    23.     i815
    24.     i818
    25.     i819
    26.     i820
    27.     i824
    28.     i826
    29.     i829
    30.     i834
    31.     i849
    32.     i856
    33.     i862
    34.     i863
    35.     i869
    36.     i870
    37.     i871
    38.     i872
    39.     i874
    40.     i878
    41.     i879
    42.     i883
    43.     i889
    44.     i890
    45.     i893
    46.     i896
    47.     i897
    48.     i898
    49.     i899
    50.     i900
    51.     i903
    52.     i904
    53.     i916
    54.     i929
    55.     i930
    56.     i932
    57.     i933
    58.     i936
    59.     i940
  3. 3Silicon Limitations
    1.     Revisions SR 1.0 - Limitations List
    2.     i596
    3.     i641
    4.     i833
    5.     i838
    6.     i844
    7.     i845
    8.     i848
    9.     i876
    10.     i877
    11.     i892
    12.     i909
  4. 4Silicon Cautions
    1.     Revisions SR 1.0 - Cautions List
    2.     i781
    3.     i827
    4.     i832
    5.     i836
    6.     i839
    7.     i864
    8.     i885
    9.     i886
    10.     i912
    11.     i926
    12.     i931
    13.     i935
    14.     i937
  5. 5Revision History

i824

USB3.0 Link Cannot Be Established When Suspend Mode Is Enabled

CRITICALITY

Medium

DESCRIPTION

When suspend mode is enabled (USB_GUSB3PIPECTL[17]SUSPENDENABLE =0x1), the communication between the host controller and the USB device is broken. This happens in the following two sequences:

Sequence 1:

  • Enable and configure the DWC_USB3 controller as host
  • Set the USB_GUSB3PIPECTL[17]SUSPENDENABLE = 0x1 and USB_GUSB2PHYCFG[6]SUSPHY = 0x1
  • Connect a USB3.0 device

When USB3.0 device is connected there is not enough time to establish the USB3.0 link so the host controller falls back to USB2.0 mode.

Sequence 2:

  • Enable and configure the DWC_USB3 controller as host
  • Wait until the USB3.0 link is established
  • Set the USB_GUSB3PIPECTL [17]SUSPENDENABLE = 0x1 and USB_GUSB2PHYCFG [6]SUSPHY = 0x1
  • Host controller initiates a transition to U3.
  • Wait until transition U3 is completed successfully
  • Host controller initiates a transition to U0.

The USB3.0 link cannot be reestablished and the host controller falls back to USB2.0.

WORKAROUND

First set CTRL_CORE_PHY_POWER_USB[21:14]USB_PWRCTL_CLK_CMD to 0x43 then to 0x03 just after U3_EXIT state (setting the PORTSC2 in U0 by Polling on USB_PORTSC2 [8:5]PLS=RESUME) and before Recovery state.

REVISIONS IMPACTED

SR 1.0

AM574x: 1.0

DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0

TDA2Px: 1.0

AM576x: 1.0