SPRZ450A February 2018 – October 2019 DRA74P , DRA75P , DRA76P , DRA77P
SATA PHY Reset Required Following SATA PLL Unlock
Medium
If SATA controller is in slumber or partial low-power mode, SATA PHY is in low-power mode, and SATA 1.5 GHz PLL is relocked for any reason, the PHY receiver looses lock. In result the receiver / de-serializer is unable to produce parallel data from a correct serial source, and will not detect the attached SATA drive.
Workaround is to disable and re-enable both analog LDO of the transceiver, using the corresponding SW programmable bits of power control MMR: The CTRL_CORE_PHY_POWER_SATA[21:14] SATA_PWRCTL_CLK_CMD must be set to 0x0 to power down the SATA PHY TX and RX modules.
The rest of the workaround sequence is the same as upon initial SATA PHY power-up, and includes setting above bits back to 0x2.
SR 1.0
AM574x: 1.0
DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0
TDA2Px: 1.0
AM576x: 1.0