SPRUIX1B October   2022  â€“ April 2024 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000â„¢ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studioâ„¢ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit
    5. 2.5 Trigonometric Math Unit (TMU)
  5. 3 System Control and Interrupts
    1. 3.1  Introduction
      1. 3.1.1 SYSCTL Related Collateral
      2. 3.1.2 LOCK Protection on System Configuration Registers
      3. 3.1.3 EALLOW Protection
    2. 3.2  Power Management
    3. 3.3  Device Identification and Configuration Registers
    4. 3.4  Resets
      1. 3.4.1  Reset Sources
      2. 3.4.2  External Reset (XRS)
      3. 3.4.3  Simulate External Reset (SIMRESET.XRS)
      4. 3.4.4  Power-On Reset (POR)
      5. 3.4.5  Brown-Out-Reset (BOR)
      6. 3.4.6  Debugger Reset (SYSRS)
      7. 3.4.7  Simulate CPU Reset
      8. 3.4.8  Watchdog Reset (WDRS)
      9. 3.4.9  NMI Watchdog Reset (NMIWDRS)
      10. 3.4.10 DCSM Safe Code Copy Reset (SCCRESET)
    5. 3.5  Peripheral Interrupts
      1. 3.5.1 Interrupt Concepts
      2. 3.5.2 Interrupt Architecture
        1. 3.5.2.1 Peripheral Stage
        2. 3.5.2.2 PIE Stage
        3. 3.5.2.3 CPU Stage
      3. 3.5.3 Interrupt Entry Sequence
      4. 3.5.4 Configuring and Using Interrupts
        1. 3.5.4.1 Enabling Interrupts
        2. 3.5.4.2 Handling Interrupts
        3. 3.5.4.3 Disabling Interrupts
        4. 3.5.4.4 Nesting Interrupts
        5. 3.5.4.5 Vector Address Validity Check
      5. 3.5.5 PIE Channel Mapping
      6. 3.5.6 PIE Interrupt Priority
        1. 3.5.6.1 Channel Priority
        2. 3.5.6.2 Group Priority
      7. 3.5.7 System Error
      8. 3.5.8 Vector Tables
    6. 3.6  Exceptions and Non-Maskable Interrupts
      1. 3.6.1 Configuring and Using NMIs
      2. 3.6.2 Emulation Considerations
      3. 3.6.3 NMI Sources
        1. 3.6.3.1 Missing Clock Detection
        2. 3.6.3.2 RAM Uncorrectable Error
        3. 3.6.3.3 Flash Uncorrectable ECC Error
        4. 3.6.3.4 Software-Forced Error
      4. 3.6.4 Illegal Instruction Trap (ITRAP)
      5. 3.6.5 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1  Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
          1. 3.7.1.1.1 External Resistor (ExtR) Mode
            1. 3.7.1.1.1.1 INTOSC2 with External Precision Resistor – ExtR
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 Auxiliary Clock Input (AUXCLKIN)
        4. 3.7.1.4 External Oscillator (XTAL)
      2. 3.7.2  Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.7.3  Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 CAN Bit Clock
        6. 3.7.3.6 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4  XCLKOUT
      5. 3.7.5  Clock Connectivity
      6. 3.7.6  Clock Source and PLL Setup
      7. 3.7.7  Using an External Crystal or Resonator
      8. 3.7.8  Using an External Oscillator
      9. 3.7.9  Using an External Resistor (ExtR) With Internal Oscillator
      10. 3.7.10 Choosing PLL Settings
      11. 3.7.11 System Clock Setup
      12. 3.7.12 SYS PLL Bypass
      13. 3.7.13 Clock (OSCCLK) Failure Detection
        1. 3.7.13.1 Missing Clock Detection
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timer
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low Power Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 Clock-Gating Low-Power Modes
      2. 3.10.2 IDLE
      3. 3.10.3 STANDBY
      4. 3.10.4 HALT
    11. 3.11 Memory Controller Module
      1. 3.11.1 Functional Description
        1. 3.11.1.1 Dedicated RAM (Mx RAM)
        2. 3.11.1.2 Local Shared RAM (LSx RAM)
        3. 3.11.1.3 Access Protection
          1. 3.11.1.3.1 CPU Fetch Protection
          2. 3.11.1.3.2 CPU Write Protection
          3. 3.11.1.3.3 CPU Read Protection
        4. 3.11.1.4 Memory Error Detection, Correction, and Error Handling
          1. 3.11.1.4.1 Error Detection and Correction
          2. 3.11.1.4.2 Error Handling
        5. 3.11.1.5 Application Test Hooks for Error Detection and Correction
        6. 3.11.1.6 RAM Initialization
    12. 3.12 JTAG
      1. 3.12.1 JTAG Noise and TAP_STATUS
    13. 3.13 System Control Register Configuration Restrictions
    14. 3.14 Software
      1. 3.14.1 SYSCTL Examples
        1. 3.14.1.1 Missing clock detection (MCD)
        2. 3.14.1.2 XCLKOUT (External Clock Output) Configuration
      2. 3.14.2 TIMER Examples
        1. 3.14.2.1 CPU Timers
        2. 3.14.2.2 CPU Timers
      3. 3.14.3 MEMCFG Examples
        1. 3.14.3.1 Correctable & Uncorrectable Memory Error Handling
      4. 3.14.4 INTERRUPT Examples
        1. 3.14.4.1 External Interrupts (ExternalInterrupt)
        2. 3.14.4.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
        3. 3.14.4.3 CPU Timer Interrupt Software Prioritization
        4. 3.14.4.4 EPWM Real-Time Interrupt
      5. 3.14.5 LPM Examples
        1. 3.14.5.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO
        2. 3.14.5.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog
        3. 3.14.5.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO
        4. 3.14.5.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog
        5. 3.14.5.5 Low Power Modes: Halt Mode and Wakeup using GPIO
        6. 3.14.5.6 Low Power Modes: Halt Mode and Wakeup
      6. 3.14.6 WATCHDOG Examples
        1. 3.14.6.1 Watchdog
    15. 3.15 System Control Registers
      1. 3.15.1  SYSCTRL Base Address Table
      2. 3.15.2  ACCESS_PROTECTION_REGS Registers
      3. 3.15.3  CLK_CFG_REGS Registers
      4. 3.15.4  CPU_SYS_REGS Registers
      5. 3.15.5  CPUTIMER_REGS Registers
      6. 3.15.6  DEV_CFG_REGS Registers
      7. 3.15.7  MEM_CFG_REGS Registers
      8. 3.15.8  MEMORY_ERROR_REGS Registers
      9. 3.15.9  NMI_INTRUPT_REGS Registers
      10. 3.15.10 PIE_CTRL_REGS Registers
      11. 3.15.11 SYNC_SOC_REGS Registers
      12. 3.15.12 SYS_STATUS_REGS Registers
      13. 3.15.13 TEST_ERROR_REGS Registers
      14. 3.15.14 UID_REGS Registers
      15. 3.15.15 WD_REGS Registers
      16. 3.15.16 XINT_REGS Registers
      17. 3.15.17 Register to Driverlib Function Mapping
        1. 3.15.17.1 ASYSCTL Registers to Driverlib Functions
        2. 3.15.17.2 CPUTIMER Registers to Driverlib Functions
        3. 3.15.17.3 MEMCFG Registers to Driverlib Functions
        4. 3.15.17.4 NMI Registers to Driverlib Functions
        5. 3.15.17.5 PIE Registers to Driverlib Functions
        6. 3.15.17.6 SYSCTL Registers to Driverlib Functions
        7. 3.15.17.7 XINT Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Boot Flow
      2. 4.5.2 Emulation Boot Flow
      3. 4.5.3 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 GPREG2 Usage and MPOST Configuration
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Secure Flash Boot
        1. 4.7.4.1 Secure Flash CPU1 Linker File Example
      5. 4.7.5  Memory Maps
        1. 4.7.5.1 Boot ROM Memory Maps
        2. 4.7.5.2 Reserved RAM Memory Maps
      6. 4.7.6  ROM Tables
      7. 4.7.7  Boot Modes and Loaders
        1. 4.7.7.1 Boot Modes
          1. 4.7.7.1.1 Flash Boot
          2. 4.7.7.1.2 RAM Boot
          3. 4.7.7.1.3 Wait Boot
        2. 4.7.7.2 Bootloaders
          1. 4.7.7.2.1 SCI Boot Mode
          2. 4.7.7.2.2 SPI Boot Mode
          3. 4.7.7.2.3 I2C Boot Mode
          4. 4.7.7.2.4 Parallel Boot Mode
          5. 4.7.7.2.5 CAN Boot Mode
      8. 4.7.8  GPIO Assignments
      9. 4.7.9  Secure ROM Function APIs
      10. 4.7.10 Clock Initializations
      11. 4.7.11 Boot Status Information
        1. 4.7.11.1 Booting Status
        2. 4.7.11.2 Boot Mode and MPOST (Memory Power On Self-Test) Status
      12. 4.7.12 ROM Version
    8. 4.8 Application Notes for Using the Bootloaders
      1. 4.8.1 Bootloader Data Stream Structure
        1. 4.8.1.1 Data Stream Structure 8-bit
      2. 4.8.2 The C2000 Hex Utility
        1. 4.8.2.1 HEX2000.exe Command Syntax
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Execute-Only Protection
      5. 5.2.5 Password Lock
      6. 5.2.6 JTAGLOCK
      7. 5.2.7 Link Pointer and Zone Select
      8. 5.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
      1. 5.6.1 RAMOPEN
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Examples
        1. 5.8.1.1 Empty DCSM Tool Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
      7. 5.9.7 DCSM Registers to Driverlib Functions
  8. 6 Flash Module
    1. 6.1  Introduction to Flash and OTP Memory
      1. 6.1.1 FLASH Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Flash Tools
      4. 6.1.4 Default Flash Configuration
    2. 6.2  Flash Bank, OTP, and Pump
    3. 6.3  Flash Wrapper
    4. 6.4  Flash and OTP Memory Performance
    5. 6.5  Flash Read Interface
      1. 6.5.1 C28x-Flash Read Interface
        1. 6.5.1.1 Standard Read Mode
        2. 6.5.1.2 Prefetch Mode
        3. 6.5.1.3 Data Cache
        4. 6.5.1.4 Flash Read Operation
    6. 6.6  Flash Erase and Program
      1. 6.6.1 Erase
      2. 6.6.2 Program
      3. 6.6.3 Verify
    7. 6.7  Error Correction Code (ECC) Protection
      1. 6.7.1 Single-Bit Data Error
      2. 6.7.2 Uncorrectable Error
      3. 6.7.3 Mechanism to Check the Correctness of ECC Logic
    8. 6.8  Reserved Locations Within Flash and OTP
    9. 6.9  Migrating an Application from RAM to Flash
    10. 6.10 Procedure to Change the Flash Control Registers
    11. 6.11 Software
      1. 6.11.1 FLASH Examples
        1. 6.11.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
        2. 6.11.1.2 Boot Source Code
        3. 6.11.1.3 Erase Source Code
        4. 6.11.1.4 Live DFU Command Functionality
        5. 6.11.1.5 Verify Source Code
        6. 6.11.1.6 SCI Boot Mode Routines
        7. 6.11.1.7 Flash Programming Solution using SCI
    12. 6.12 Flash Registers
      1. 6.12.1 FLASH Base Address Table
      2. 6.12.2 FLASH_CTRL_REGS Registers
      3. 6.12.3 FLASH_ECC_REGS Registers
      4. 6.12.4 FLASH Registers to Driverlib Functions
  9. 7 Dual-Clock Comparator (DCC)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 Block Diagram
    2. 7.2 Module Operation
      1. 7.2.1 Configuring DCC Counters
      2. 7.2.2 Single-Shot Measurement Mode
      3. 7.2.3 Continuous Monitoring Mode
      4. 7.2.4 Error Conditions
    3. 7.3 Interrupts
    4. 7.4 Software
      1. 7.4.1 DCC Examples
        1. 7.4.1.1 DCC Single shot Clock verification
        2. 7.4.1.2 DCC Single shot Clock measurement
        3. 7.4.1.3 DCC Continuous clock monitoring
        4. 7.4.1.4 DCC Continuous clock monitoring
        5. 7.4.1.5 DCC Detection of clock failure
    5. 7.5 DCC Registers
      1. 7.5.1 DCC Base Address Table
      2. 7.5.2 DCC_REGS Registers
      3. 7.5.3 DCC Registers to Driverlib Functions
  10. 8 General-Purpose Input/Output (GPIO)
    1. 8.1  Introduction
      1. 8.1.1 GPIO Related Collateral
    2. 8.2  Configuration Overview
    3. 8.3  Digital Inputs on ADC Pins (AIOs)
    4. 8.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 8.5  Digital General-Purpose I/O Control
    6. 8.6  Input Qualification
      1. 8.6.1 No Synchronization (Asynchronous Input)
      2. 8.6.2 Synchronization to SYSCLKOUT Only
      3. 8.6.3 Qualification Using a Sampling Window
    7. 8.7  GPIO and Peripheral Muxing
      1. 8.7.1 GPIO Muxing
      2. 8.7.2 Peripheral Muxing
    8. 8.8  Internal Pullup Configuration Requirements
    9. 8.9  Software
      1. 8.9.1 GPIO Examples
        1. 8.9.1.1 Device GPIO Setup
        2. 8.9.1.2 Device GPIO Toggle
        3. 8.9.1.3 Device GPIO Interrupt
        4. 8.9.1.4 External Interrupt (XINT)
      2. 8.9.2 LED Examples
    10. 8.10 GPIO Registers
      1. 8.10.1 GPIO Base Address Table
      2. 8.10.2 GPIO_CTRL_REGS Registers
      3. 8.10.3 GPIO_DATA_REGS Registers
      4. 8.10.4 GPIO_DATA_READ_REGS Registers
      5. 8.10.5 GPIO Registers to Driverlib Functions
  11. 9 Crossbar (X-BAR)
    1. 9.1 Input X-BAR
    2. 9.2 ePWM and GPIO Output X-BAR
      1. 9.2.1 ePWM X-BAR
        1. 9.2.1.1 ePWM X-BAR Architecture
      2. 9.2.2 GPIO Output X-BAR
        1. 9.2.2.1 GPIO Output X-BAR Architecture
      3. 9.2.3 X-BAR Flags
    3. 9.3 XBAR Registers
      1. 9.3.1 XBAR Base Address Table
      2. 9.3.2 INPUT_XBAR_REGS Registers
      3. 9.3.3 XBAR_REGS Registers
      4. 9.3.4 EPWM_XBAR_REGS Registers
      5. 9.3.5 OUTPUT_XBAR_REGS Registers
      6. 9.3.6 Register to Driverlib Function Mapping
        1. 9.3.6.1 INPUTXBAR Registers to Driverlib Functions
        2. 9.3.6.2 XBAR Registers to Driverlib Functions
        3. 9.3.6.3 EPWMXBAR Registers to Driverlib Functions
        4. 9.3.6.4 OUTPUTXBAR Registers to Driverlib Functions
  12. 10Analog Subsystem
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Optimizing Power-Up Time
    3. 10.3 Digital Inputs on ADC Pins (AIOs)
    4. 10.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 10.5 Analog Pins and Internal Connections
    6. 10.6 Analog Subsystem Registers
      1. 10.6.1 ASBSYS Base Address Table
      2. 10.6.2 ANALOG_SUBSYS_REGS Registers
  13. 11Analog-to-Digital Converter (ADC)
    1. 11.1  Introduction
      1. 11.1.1 ADC Related Collateral
      2. 11.1.2 Features
      3. 11.1.3 Block Diagram
    2. 11.2  ADC Configurability
      1. 11.2.1 Clock Configuration
      2. 11.2.2 Resolution
      3. 11.2.3 Voltage Reference
        1. 11.2.3.1 External Reference Mode
        2. 11.2.3.2 Internal Reference Mode
        3. 11.2.3.3 Selecting Reference Mode
      4. 11.2.4 Signal Mode
      5. 11.2.5 Expected Conversion Results
      6. 11.2.6 Interpreting Conversion Results
    3. 11.3  SOC Principle of Operation
      1. 11.3.1 SOC Configuration
      2. 11.3.2 Trigger Operation
      3. 11.3.3 ADC Acquisition (Sample and Hold) Window
      4. 11.3.4 ADC Input Models
      5. 11.3.5 Channel Selection
    4. 11.4  SOC Configuration Examples
      1. 11.4.1 Single Conversion from ePWM Trigger
      2. 11.4.2 Oversampled Conversion from ePWM Trigger
      3. 11.4.3 Multiple Conversions from CPU Timer Trigger
      4. 11.4.4 Software Triggering of SOCs
    5. 11.5  ADC Conversion Priority
    6. 11.6  Burst Mode
      1. 11.6.1 Burst Mode Example
      2. 11.6.2 Burst Mode Priority Example
    7. 11.7  EOC and Interrupt Operation
      1. 11.7.1 Interrupt Overflow
      2. 11.7.2 Continue to Interrupt Mode
      3. 11.7.3 Early Interrupt Configuration Mode
    8. 11.8  Post-Processing Blocks
      1. 11.8.1 PPB Offset Correction
      2. 11.8.2 PPB Error Calculation
      3. 11.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 11.8.4 PPB Sample Delay Capture
    9. 11.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 11.9.1 Implementation
      2. 11.9.2 Detecting an Open Input Pin
      3. 11.9.3 Detecting a Shorted Input Pin
    10. 11.10 Power-Up Sequence
    11. 11.11 ADC Calibration
      1. 11.11.1 ADC Zero Offset Calibration
    12. 11.12 ADC Timings
      1. 11.12.1 ADC Timing Diagrams
    13. 11.13 Additional Information
      1. 11.13.1 Ensuring Synchronous Operation
        1. 11.13.1.1 Basic Synchronous Operation
        2. 11.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 11.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 11.13.1.4 Non-overlapping Conversions
      2. 11.13.2 Choosing an Acquisition Window Duration
      3. 11.13.3 Achieving Simultaneous Sampling
      4. 11.13.4 Result Register Mapping
      5. 11.13.5 Internal Temperature Sensor
      6. 11.13.6 Designing an External Reference Circuit
      7. 11.13.7 ADC-DAC Loopback Testing
      8. 11.13.8 Internal Test Mode
      9. 11.13.9 ADC Gain and Offset Calibration
    14. 11.14 Software
      1. 11.14.1 ADC Examples
        1. 11.14.1.1  ADC Software Triggering
        2. 11.14.1.2  ADC ePWM Triggering
        3. 11.14.1.3  ADC Temperature Sensor Conversion
        4. 11.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 11.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 11.14.1.6  ADC PPB Offset (adc_ppb_offset)
        7. 11.14.1.7  ADC PPB Limits (adc_ppb_limits)
        8. 11.14.1.8  ADC PPB Delay Capture (adc_ppb_delay)
        9. 11.14.1.9  ADC ePWM Triggering Multiple SOC
        10. 11.14.1.10 ADC Burst Mode
        11. 11.14.1.11 ADC Burst Mode Oversampling
        12. 11.14.1.12 ADC SOC Oversampling
        13. 11.14.1.13 ADC PPB PWM trip (adc_ppb_pwm_trip)
        14. 11.14.1.14 ADC Open Shorts Detection (adc_open_shorts_detection)
    15. 11.15 ADC Registers
      1. 11.15.1 ADC Base Address Table
      2. 11.15.2 ADC_RESULT_REGS Registers
      3. 11.15.3 ADC_REGS Registers
      4. 11.15.4 ADC Registers to Driverlib Functions
  14. 12Comparator Subsystem (CMPSS)
    1. 12.1 Introduction
      1. 12.1.1 CMPSS Related Collateral
      2. 12.1.2 Features
      3. 12.1.3 CMPSS Module Variants
      4. 12.1.4 Block Diagram
    2. 12.2 Comparator
    3. 12.3 Reference DAC
    4. 12.4 Ramp Generator
      1. 12.4.1 Ramp Generator Overview
      2. 12.4.2 Ramp Generator Behavior
      3. 12.4.3 Ramp Generator Behavior at Corner Cases
    5. 12.5 Digital Filter
      1. 12.5.1 Filter Initialization Sequence
    6. 12.6 Using the CMPSS
      1. 12.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 12.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 12.6.3 Calibrating the CMPSS
      4. 12.6.4 Enabling and Disabling the CMPSS Clock
    7. 12.7 CMPSS DAC Output
    8. 12.8 Software
      1. 12.8.1 CMPSS Examples
        1. 12.8.1.1 CMPSS Asynchronous Trip
        2. 12.8.1.2 CMPSS Digital Filter Configuration
      2. 12.8.2 CMPSS_LITE Examples
        1. 12.8.2.1 CMPSSLITE Asynchronous Trip
    9. 12.9 CMPSS Registers
      1. 12.9.1 CMPSS Base Address Table
      2. 12.9.2 CMPSS_REGS Registers
      3. 12.9.3 CMPSS_LITE_REGS Registers
      4. 12.9.4 CMPSS Registers to Driverlib Functions
      5. 12.9.5 CMPSS_LITE Registers to Driverlib Functions
  15. 13Enhanced Pulse Width Modulator (ePWM)
    1. 13.1  Introduction
      1. 13.1.1 EPWM Related Collateral
      2. 13.1.2 Submodule Overview
    2. 13.2  Configuring Device Pins
    3. 13.3  ePWM Modules Overview
    4. 13.4  Time-Base (TB) Submodule
      1. 13.4.1 Purpose of the Time-Base Submodule
      2. 13.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 13.4.3 Calculating PWM Period and Frequency
        1. 13.4.3.1 Time-Base Period Shadow Register
        2. 13.4.3.2 Time-Base Clock Synchronization
        3. 13.4.3.3 Time-Base Counter Synchronization
        4. 13.4.3.4 ePWM SYNC Selection
      4. 13.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 13.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 13.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 13.4.7 Global Load
        1. 13.4.7.1 Global Load Pulse Pre-Scalar
        2. 13.4.7.2 One-Shot Load Mode
        3. 13.4.7.3 One-Shot Sync Mode
    5. 13.5  Counter-Compare (CC) Submodule
      1. 13.5.1 Purpose of the Counter-Compare Submodule
      2. 13.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 13.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 13.5.4 Count Mode Timing Waveforms
    6. 13.6  Action-Qualifier (AQ) Submodule
      1. 13.6.1 Purpose of the Action-Qualifier Submodule
      2. 13.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 13.6.3 Action-Qualifier Event Priority
      4. 13.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 13.6.5 Configuration Requirements for Common Waveforms
    7. 13.7  Dead-Band Generator (DB) Submodule
      1. 13.7.1 Purpose of the Dead-Band Submodule
      2. 13.7.2 Dead-band Submodule Additional Operating Modes
      3. 13.7.3 Operational Highlights for the Dead-Band Submodule
    8. 13.8  PWM Chopper (PC) Submodule
      1. 13.8.1 Purpose of the PWM Chopper Submodule
      2. 13.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 13.8.3 Waveforms
        1. 13.8.3.1 One-Shot Pulse
        2. 13.8.3.2 Duty Cycle Control
    9. 13.9  Trip-Zone (TZ) Submodule
      1. 13.9.1 Purpose of the Trip-Zone Submodule
      2. 13.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 13.9.2.1 Trip-Zone Configurations
      3. 13.9.3 Generating Trip Event Interrupts
    10. 13.10 Event-Trigger (ET) Submodule
      1. 13.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 13.11 Digital Compare (DC) Submodule
      1. 13.11.1 Purpose of the Digital Compare Submodule
      2. 13.11.2 Enhanced Trip Action Using CMPSS
      3. 13.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 13.11.4 Operation Highlights of the Digital Compare Submodule
        1. 13.11.4.1 Digital Compare Events
        2. 13.11.4.2 Event Filtering
        3. 13.11.4.3 Valley Switching
    12. 13.12 ePWM Crossbar (X-BAR)
    13. 13.13 Applications to Power Topologies
      1. 13.13.1  Overview of Multiple Modules
      2. 13.13.2  Key Configuration Capabilities
      3. 13.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 13.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 13.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 13.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 13.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 13.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 13.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 13.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 13.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 13.14 Register Lock Protection
    15. 13.15 High-Resolution Pulse Width Modulator (HRPWM)
      1. 13.15.1 Operational Description of HRPWM
        1. 13.15.1.1 Controlling the HRPWM Capabilities
        2. 13.15.1.2 HRPWM Source Clock
        3. 13.15.1.3 Configuring the HRPWM
        4. 13.15.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 13.15.1.5 Principle of Operation
          1. 13.15.1.5.1 Edge Positioning
          2. 13.15.1.5.2 Scaling Considerations
          3. 13.15.1.5.3 Duty Cycle Range Limitation
          4. 13.15.1.5.4 High-Resolution Period
            1. 13.15.1.5.4.1 High-Resolution Period Configuration
        6. 13.15.1.6 Deadband High-Resolution Operation
        7. 13.15.1.7 Scale Factor Optimizing Software (SFO)
        8. 13.15.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 13.15.1.8.1 #Defines for HRPWM Header Files
          2. 13.15.1.8.2 Implementing a Simple Buck Converter
            1. 13.15.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 13.15.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 13.15.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 13.15.1.8.3.1 PWM DAC Function Initialization Code
            2. 13.15.1.8.3.2 PWM DAC Function Run-Time Code
      2. 13.15.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 13.15.2.1 Scale Factor Optimizer Function - int SFO()
        2. 13.15.2.2 Software Usage
          1. 13.15.2.2.1 A Sample of How to Add "Include" Files
          2.        599
          3. 13.15.2.2.2 Declaring an Element
          4.        601
          5. 13.15.2.2.3 Initializing With a Scale Factor Value
          6.        603
          7. 13.15.2.2.4 SFO Function Calls
    16. 13.16 Software
      1. 13.16.1 EPWM Examples
        1. 13.16.1.1  ePWM Trip Zone
        2. 13.16.1.2  ePWM Up Down Count Action Qualifier
        3. 13.16.1.3  ePWM Synchronization
        4. 13.16.1.4  ePWM Digital Compare
        5. 13.16.1.5  ePWM Digital Compare Event Filter Blanking Window
        6. 13.16.1.6  ePWM Valley Switching
        7. 13.16.1.7  ePWM Digital Compare Edge Filter
        8. 13.16.1.8  ePWM Deadband
        9. 13.16.1.9  ePWM Chopper
        10. 13.16.1.10 EPWM Configure Signal
        11. 13.16.1.11 Realization of Monoshot mode
        12. 13.16.1.12 EPWM Action Qualifier (epwm_up_aq)
      2. 13.16.2 HRPWM Examples
        1. 13.16.2.1 HRPWM Duty Control with SFO
        2. 13.16.2.2 HRPWM Slider
        3. 13.16.2.3 HRPWM Period Control
        4. 13.16.2.4 HRPWM Duty Control with UPDOWN Mode
        5. 13.16.2.5 HRPWM Slider Test
        6. 13.16.2.6 HRPWM Duty Up Count
        7. 13.16.2.7 HRPWM Period Up-Down Count
    17. 13.17 ePWM Registers
      1. 13.17.1 EPWM Base Address Table
      2. 13.17.2 EPWM_REGS Registers
      3. 13.17.3 Register to Driverlib Function Mapping
        1. 13.17.3.1 EPWM Registers to Driverlib Functions
        2. 13.17.3.2 HRPWM Registers to Driverlib Functions
  16. 14Enhanced Capture (eCAP)
    1. 14.1 Introduction
      1. 14.1.1 Features
      2. 14.1.2 ECAP Related Collateral
    2. 14.2 Description
    3. 14.3 Configuring Device Pins for the eCAP
    4. 14.4 Capture and APWM Operating Mode
    5. 14.5 Capture Mode Description
      1. 14.5.1 Event Prescaler
      2. 14.5.2 Edge Polarity Select and Qualifier
      3. 14.5.3 Continuous/One-Shot Control
      4. 14.5.4 32-Bit Counter and Phase Control
      5. 14.5.5 CAP1-CAP4 Registers
      6. 14.5.6 eCAP Synchronization
        1. 14.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 14.5.7 Interrupt Control
      8. 14.5.8 Shadow Load and Lockout Control
      9. 14.5.9 APWM Mode Operation
    6. 14.6 Application of the eCAP Module
      1. 14.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 14.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 14.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 14.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 14.7 Application of the APWM Mode
      1. 14.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 14.8 Software
      1. 14.8.1 ECAP Examples
        1. 14.8.1.1 eCAP APWM Example
        2. 14.8.1.2 eCAP Capture PWM Example
        3. 14.8.1.3 eCAP APWM Phase-shift Example
    9. 14.9 eCAP Registers
      1. 14.9.1 ECAP Base Address Table
      2. 14.9.2 ECAP_REGS Registers
      3. 14.9.3 ECAP Registers to Driverlib Functions
  17. 15Enhanced Quadrature Encoder Pulse (eQEP)
    1. 15.1  Introduction
      1. 15.1.1 EQEP Related Collateral
    2. 15.2  Configuring Device Pins
    3. 15.3  Description
      1. 15.3.1 EQEP Inputs
      2. 15.3.2 Functional Description
      3. 15.3.3 eQEP Memory Map
    4. 15.4  Quadrature Decoder Unit (QDU)
      1. 15.4.1 Position Counter Input Modes
        1. 15.4.1.1 Quadrature Count Mode
        2. 15.4.1.2 Direction-Count Mode
        3. 15.4.1.3 Up-Count Mode
        4. 15.4.1.4 Down-Count Mode
      2. 15.4.2 eQEP Input Polarity Selection
      3. 15.4.3 Position-Compare Sync Output
    5. 15.5  Position Counter and Control Unit (PCCU)
      1. 15.5.1 Position Counter Operating Modes
        1. 15.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 15.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 15.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 15.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 15.5.2 Position Counter Latch
        1. 15.5.2.1 Index Event Latch
        2. 15.5.2.2 Strobe Event Latch
      3. 15.5.3 Position Counter Initialization
      4. 15.5.4 eQEP Position-compare Unit
    6. 15.6  eQEP Edge Capture Unit
    7. 15.7  eQEP Watchdog
    8. 15.8  eQEP Unit Timer Base
    9. 15.9  QMA Module
      1. 15.9.1 Modes of Operation
        1. 15.9.1.1 QMA Mode-1 (QMACTRL[MODE]=1)
        2. 15.9.1.2 QMA Mode-2 (QMACTRL[MODE]=2)
      2. 15.9.2 Interrupt and Error Generation
    10. 15.10 eQEP Interrupt Structure
    11. 15.11 Software
      1. 15.11.1 EQEP Examples
        1. 15.11.1.1 Frequency Measurement Using eQEP
        2. 15.11.1.2 Position and Speed Measurement Using eQEP
        3. 15.11.1.3 ePWM frequency Measurement Using eQEP via xbar connection
        4. 15.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 15.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 15.12 eQEP Registers
      1. 15.12.1 EQEP Base Address Table
      2. 15.12.2 EQEP_REGS Registers
      3. 15.12.3 EQEP Registers to Driverlib Functions
  18. 16Controller Area Network (CAN)
    1. 16.1  Introduction
      1. 16.1.1 DCAN Related Collateral
      2. 16.1.2 Features
      3. 16.1.3 Block Diagram
        1. 16.1.3.1 CAN Core
        2. 16.1.3.2 Message Handler
        3. 16.1.3.3 Message RAM
        4. 16.1.3.4 Registers and Message Object Access (IFx)
    2. 16.2  Functional Description
      1. 16.2.1 Configuring Device Pins
      2. 16.2.2 Address/Data Bus Bridge
    3. 16.3  Operating Modes
      1. 16.3.1 Initialization
      2. 16.3.2 CAN Message Transfer (Normal Operation)
        1. 16.3.2.1 Disabled Automatic Retransmission
        2. 16.3.2.2 Auto-Bus-On
      3. 16.3.3 Test Modes
        1. 16.3.3.1 Silent Mode
        2. 16.3.3.2 Loopback Mode
        3. 16.3.3.3 External Loopback Mode
        4. 16.3.3.4 Loopback Combined with Silent Mode
    4. 16.4  Multiple Clock Source
    5. 16.5  Interrupt Functionality
      1. 16.5.1 Message Object Interrupts
      2. 16.5.2 Status Change Interrupts
      3. 16.5.3 Error Interrupts
      4. 16.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 16.5.5 Interrupt Topologies
    6. 16.6  Parity Check Mechanism
      1. 16.6.1 Behavior on Parity Error
    7. 16.7  Debug Mode
    8. 16.8  Module Initialization
    9. 16.9  Configuration of Message Objects
      1. 16.9.1 Configuration of a Transmit Object for Data Frames
      2. 16.9.2 Configuration of a Transmit Object for Remote Frames
      3. 16.9.3 Configuration of a Single Receive Object for Data Frames
      4. 16.9.4 Configuration of a Single Receive Object for Remote Frames
      5. 16.9.5 Configuration of a FIFO Buffer
    10. 16.10 Message Handling
      1. 16.10.1  Message Handler Overview
      2. 16.10.2  Receive/Transmit Priority
      3. 16.10.3  Transmission of Messages in Event Driven CAN Communication
      4. 16.10.4  Updating a Transmit Object
      5. 16.10.5  Changing a Transmit Object
      6. 16.10.6  Acceptance Filtering of Received Messages
      7. 16.10.7  Reception of Data Frames
      8. 16.10.8  Reception of Remote Frames
      9. 16.10.9  Reading Received Messages
      10. 16.10.10 Requesting New Data for a Receive Object
      11. 16.10.11 Storing Received Messages in FIFO Buffers
      12. 16.10.12 Reading from a FIFO Buffer
    11. 16.11 CAN Bit Timing
      1. 16.11.1 Bit Time and Bit Rate
        1. 16.11.1.1 Synchronization Segment
        2. 16.11.1.2 Propagation Time Segment
        3. 16.11.1.3 Phase Buffer Segments and Synchronization
        4. 16.11.1.4 Oscillator Tolerance Range
      2. 16.11.2 Configuration of the CAN Bit Timing
        1. 16.11.2.1 Calculation of the Bit Timing Parameters
        2. 16.11.2.2 Example for Bit Timing at High Baudrate
        3. 16.11.2.3 Example for Bit Timing at Low Baudrate
    12. 16.12 Message Interface Register Sets
      1. 16.12.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 16.12.2 Message Interface Register Set 3 (IF3)
    13. 16.13 Message RAM
      1. 16.13.1 Structure of Message Objects
      2. 16.13.2 Addressing Message Objects in RAM
      3. 16.13.3 Message RAM Representation in Debug Mode
    14. 16.14 Software
      1. 16.14.1 CAN Examples
        1. 16.14.1.1 CAN External Loopback
        2. 16.14.1.2 CAN External Loopback with Interrupts
        3. 16.14.1.3 CAN Transmit and Receive Configurations
        4. 16.14.1.4 CAN Error Generation Example
        5. 16.14.1.5 CAN Remote Request Loopback
        6. 16.14.1.6 CAN example that illustrates the usage of Mask registers
    15. 16.15 CAN Registers
      1. 16.15.1 CAN Base Address Table
      2. 16.15.2 CAN_REGS Registers
      3. 16.15.3 CAN Registers to Driverlib Functions
  19. 17Inter-Integrated Circuit Module (I2C)
    1. 17.1 Introduction
      1. 17.1.1 I2C Related Collateral
      2. 17.1.2 Features
      3. 17.1.3 Features Not Supported
      4. 17.1.4 Functional Overview
      5. 17.1.5 Clock Generation
      6. 17.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 17.1.6.1 Formula for the Master Clock Period
    2. 17.2 Configuring Device Pins
    3. 17.3 I2C Module Operational Details
      1. 17.3.1  Input and Output Voltage Levels
      2. 17.3.2  Selecting Pullup Resistors
      3. 17.3.3  Data Validity
      4. 17.3.4  Operating Modes
      5. 17.3.5  I2C Module START and STOP Conditions
      6. 17.3.6  Non-repeat Mode versus Repeat Mode
      7. 17.3.7  Serial Data Formats
        1. 17.3.7.1 7-Bit Addressing Format
        2. 17.3.7.2 10-Bit Addressing Format
        3. 17.3.7.3 Free Data Format
        4. 17.3.7.4 Using a Repeated START Condition
      8. 17.3.8  Clock Synchronization
      9. 17.3.9  Arbitration
      10. 17.3.10 Digital Loopback Mode
      11. 17.3.11 NACK Bit Generation
    4. 17.4 Interrupt Requests Generated by the I2C Module
      1. 17.4.1 Basic I2C Interrupt Requests
      2. 17.4.2 I2C FIFO Interrupts
    5. 17.5 Resetting or Disabling the I2C Module
    6. 17.6 Software
      1. 17.6.1 I2C Examples
        1. 17.6.1.1 C28x-I2C Library source file for FIFO interrupts
        2. 17.6.1.2 C28x-I2C Library source file for FIFO using polling
        3. 17.6.1.3 C28x-I2C Library source file for FIFO interrupts
        4. 17.6.1.4 I2C Digital Loopback with FIFO Interrupts
        5. 17.6.1.5 I2C EEPROM
        6. 17.6.1.6 I2C Digital External Loopback with FIFO Interrupts
        7. 17.6.1.7 I2C EEPROM
        8. 17.6.1.8 I2C controller target communication using FIFO interrupts
        9. 17.6.1.9 I2C EEPROM
    7. 17.7 I2C Registers
      1. 17.7.1 I2C Base Address Table
      2. 17.7.2 I2C_REGS Registers
      3. 17.7.3 I2C Registers to Driverlib Functions
  20. 18Serial Communications Interface (SCI)
    1. 18.1  Introduction
      1. 18.1.1 Features
      2. 18.1.2 SCI Related Collateral
      3. 18.1.3 Block Diagram
    2. 18.2  Architecture
    3. 18.3  SCI Module Signal Summary
    4. 18.4  Configuring Device Pins
    5. 18.5  Multiprocessor and Asynchronous Communication Modes
    6. 18.6  SCI Programmable Data Format
    7. 18.7  SCI Multiprocessor Communication
      1. 18.7.1 Recognizing the Address Byte
      2. 18.7.2 Controlling the SCI TX and RX Features
      3. 18.7.3 Receipt Sequence
    8. 18.8  Idle-Line Multiprocessor Mode
      1. 18.8.1 Idle-Line Mode Steps
      2. 18.8.2 Block Start Signal
      3. 18.8.3 Wake-Up Temporary (WUT) Flag
        1. 18.8.3.1 Sending a Block Start Signal
      4. 18.8.4 Receiver Operation
    9. 18.9  Address-Bit Multiprocessor Mode
      1. 18.9.1 Sending an Address
    10. 18.10 SCI Communication Format
      1. 18.10.1 Receiver Signals in Communication Modes
      2. 18.10.2 Transmitter Signals in Communication Modes
    11. 18.11 SCI Port Interrupts
      1. 18.11.1 Break Detect
    12. 18.12 SCI Baud Rate Calculations
    13. 18.13 SCI Enhanced Features
      1. 18.13.1 SCI FIFO Description
      2. 18.13.2 SCI Auto-Baud
      3. 18.13.3 Autobaud-Detect Sequence
    14. 18.14 Software
      1. 18.14.1 SCI Examples
        1. 18.14.1.1 Tune Baud Rate via UART Example
        2. 18.14.1.2 SCI FIFO Digital Loop Back
        3. 18.14.1.3 SCI Digital Loop Back with Interrupts
        4. 18.14.1.4 SCI Echoback
        5. 18.14.1.5 stdout redirect example
    15. 18.15 SCI Registers
      1. 18.15.1 SCI Base Address Table
      2. 18.15.2 SCI_REGS Registers
      3. 18.15.3 SCI Registers to Driverlib Functions
  21. 19Serial Peripheral Interface (SPI)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 SPI Related Collateral
      3. 19.1.3 Block Diagram
    2. 19.2 System-Level Integration
      1. 19.2.1 SPI Module Signals
      2. 19.2.2 Configuring Device Pins
        1. 19.2.2.1 GPIOs Required for High-Speed Mode
      3. 19.2.3 SPI Interrupts
    3. 19.3 SPI Operation
      1. 19.3.1 Introduction to Operation
      2. 19.3.2 Master Mode
      3. 19.3.3 Slave Mode
      4. 19.3.4 Data Format
        1. 19.3.4.1 Transmission of Bit from SPIRXBUF
      5. 19.3.5 Baud Rate Selection
        1. 19.3.5.1 Baud Rate Determination
        2. 19.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 19.3.6 SPI Clocking Schemes
      7. 19.3.7 SPI FIFO Description
      8. 19.3.8 SPI High-Speed Mode
      9. 19.3.9 SPI 3-Wire Mode Description
    4. 19.4 Programming Procedure
      1. 19.4.1 Initialization Upon Reset
      2. 19.4.2 Configuring the SPI
      3. 19.4.3 Configuring the SPI for High-Speed Mode
      4. 19.4.4 Data Transfer Example
      5. 19.4.5 SPI 3-Wire Mode Code Examples
        1. 19.4.5.1 3-Wire Master Mode Transmit
        2.       913
          1. 19.4.5.2.1 3-Wire Master Mode Receive
        3.       915
          1. 19.4.5.2.1 3-Wire Slave Mode Transmit
        4.       917
          1. 19.4.5.2.1 3-Wire Slave Mode Receive
      6. 19.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 19.5 Software
      1. 19.5.1 SPI Examples
        1. 19.5.1.1 SPI Digital Loopback
        2. 19.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 19.5.1.3 SPI EEPROM
    6. 19.6 SPI Registers
      1. 19.6.1 SPI Base Address Table
      2. 19.6.2 SPI_REGS Registers
      3. 19.6.3 SPI Registers to Driverlib Functions
  22. 20Embedded Pattern Generator (EPG)
    1. 20.1 Introduction
      1. 20.1.1 Features
      2. 20.1.2 EPG Block Diagram
      3. 20.1.3 EPG Related Collateral
    2. 20.2 Clock Generator Modules
      1. 20.2.1 DCLK (50% duty cycle clock)
      2. 20.2.2 Clock Stop
    3. 20.3 Signal Generator Module
    4. 20.4 EPG Peripheral Signal Mux Selection
    5. 20.5 EPG Example Use Cases
      1. 20.5.1 EPG Example: Synchronous Clocks with Offset
        1. 20.5.1.1 Synchronous Clocks with Offset Register Configuration
      2. 20.5.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 20.5.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 20.5.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 20.5.3.1 Serial Data Bit Stream (MSB first) Register Configuration
    6. 20.6 EPG Interrupt
    7. 20.7 Software
      1. 20.7.1 EPG Examples
        1. 20.7.1.1 EPG Generating Synchronous Clocks
        2. 20.7.1.2 EPG Generating Two Offset Clocks
        3. 20.7.1.3 EPG Generating Two Offset Clocks With SIGGEN
        4. 20.7.1.4 EPG Generate Serial Data
        5. 20.7.1.5 EPG Generate Serial Data Shift Mode
    8. 20.8 EPG Registers
      1. 20.8.1 EPG Base Address Table
      2. 20.8.2 EPG_REGS Registers
      3. 20.8.3 EPG_MUX_REGS Registers
      4. 20.8.4 EPG Registers to Driverlib Functions
  23. 21Revision History

3.15.7 MEM_CFG_REGS Registers

Table 3-104 lists the memory-mapped registers for the MEM_CFG_REGS registers. All register offset addresses not listed in Table 3-104 should be considered as reserved locations and the register contents should not be modified.

Table 3-104 MEM_CFG_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hDxLOCKDedicated RAM Config Lock RegisterEALLOWGo
2hDxCOMMITDedicated RAM Config Lock Commit RegisterEALLOWGo
8hDxACCPROT0Dedicated RAM Config RegisterEALLOWGo
AhDxACCPROT1Dedicated RAM Config RegisterEALLOWGo
10hDxTESTDedicated RAM TEST RegisterGo
12hDxINITDedicated RAM Init RegisterEALLOWGo
14hDxINITDONEDedicated RAM InitDone Status RegisterGo
16hDxRAMTEST_LOCKLock register to Dx RAM TEST registersGo
20hLSxLOCKLocal Shared RAM Config Lock RegisterEALLOWGo
22hLSxCOMMITLocal Shared RAM Config Lock Commit RegisterEALLOWGo
28hLSxACCPROT0Local Shared RAM Config Register 0EALLOWGo
30hLSxTESTLocal Shared RAM TEST RegisterGo
32hLSxINITLocal Shared RAM Init RegisterEALLOWGo
34hLSxINITDONELocal Shared RAM InitDone Status RegisterGo
36hLSxRAMTEST_LOCKLock register to LSx RAM TEST registersGo
A0hROM_LOCKROM Config Lock RegisterGo
A2hROM_TESTROM TEST RegisterGo
A4hROM_FORCE_ERRORROM Force Error registerGo

Complex bit access types are encoded to fit into small table cells. Table 3-105 shows the codes that are used for access types in this section.

Table 3-105 MEM_CFG_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1SW
1S		Write
1 to set
WSonceW
Sonce		Write
Set once
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

3.15.7.1 DxLOCK Register (Offset = 0h) [Reset = 00000000h]

DxLOCK is shown in Figure 3-92 and described in Table 3-106.

Return to the Summary Table.

Dedicated RAM Config Lock Register

Figure 3-92 DxLOCK Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDLOCK_PIEVECTRESERVEDRESERVEDLOCK_M1LOCK_M0
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-106 DxLOCK Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4LOCK_PIEVECTR/W0hLocks the write to access protection, master select, initialization control and test register fields for PIEVECT RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.

Reset type: SYSRSn

3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1LOCK_M1R/W0hLocks the write to access protection, master select, initialization control and test register fields for M1 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.

Reset type: SYSRSn

0LOCK_M0R/W0hLocks the write to access protection, master select, initialization control and test register fields for M0 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.

Reset type: SYSRSn

3.15.7.2 DxCOMMIT Register (Offset = 2h) [Reset = 00000000h]

DxCOMMIT is shown in Figure 3-93 and described in Table 3-107.

Return to the Summary Table.

Dedicated RAM Config Lock Commit Register

Figure 3-93 DxCOMMIT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCOMMIT_PIEVECTRESERVEDRESERVEDCOMMIT_M1COMMIT_M0
R-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-107 DxCOMMIT Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4COMMIT_PIEVECTR/WSonce0hPermanently Locks the write to access protection, master select, initialization control and test register fields for PIEVECT RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently blocked.

Reset type: SYSRSn

3RESERVEDR/WSonce0hReserved
2RESERVEDR/WSonce0hReserved
1COMMIT_M1R/WSonce0hPermanently Locks the write to access protection, master select, initialization control and test register fields for M1 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently blocked.

Reset type: SYSRSn

0COMMIT_M0R/WSonce0hPermanently Locks the write to access protection, master select, initialization control and test register fields for M0 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently blocked.

Reset type: SYSRSn

3.15.7.3 DxACCPROT0 Register (Offset = 8h) [Reset = 00000000h]

DxACCPROT0 is shown in Figure 3-94 and described in Table 3-108.

Return to the Summary Table.

Dedicated RAM Config Register

Figure 3-94 DxACCPROT0 Register
3130292827262524
RESERVEDRESERVEDRESERVED
R-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R-0hR/W-0hR/W-0h
15141312111098
RESERVEDCPUWRPROT_M1FETCHPROT_M1
R-0hR/W-0hR/W-0h
76543210
RESERVEDCPUWRPROT_M0FETCHPROT_M0
R-0hR/W-0hR/W-0h
Table 3-108 DxACCPROT0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23-18RESERVEDR0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15-10RESERVEDR0hReserved
9CPUWRPROT_M1R/W0hCPU WR Protection For M1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.

Reset type: SYSRSn

8FETCHPROT_M1R/W0hFetch Protection For M1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.

Reset type: SYSRSn

7-2RESERVEDR0hReserved
1CPUWRPROT_M0R/W0hCPU WR Protection For M0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.

Reset type: SYSRSn

0FETCHPROT_M0R/W0hFetch Protection For M0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.

Reset type: SYSRSn

3.15.7.4 DxACCPROT1 Register (Offset = Ah) [Reset = 00000000h]

DxACCPROT1 is shown in Figure 3-95 and described in Table 3-109.

Return to the Summary Table.

Dedicated RAM Config Register

Figure 3-95 DxACCPROT1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCPUWRPROT_PIEVECTRESERVED
R-0hR/W-0hR/W-0h
Table 3-109 DxACCPROT1 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1CPUWRPROT_PIEVECTR/W0hCPU Write Protection For PIEVECT RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.

Reset type: SYSRSn

0RESERVEDR/W0hReserved

3.15.7.5 DxTEST Register (Offset = 10h) [Reset = 00000000h]

DxTEST is shown in Figure 3-96 and described in Table 3-110.

Return to the Summary Table.

Dedicated RAM TEST Register

Figure 3-96 DxTEST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTEST_PIEVECT
R-0hR/W-0h
76543210
RESERVEDRESERVEDTEST_M1TEST_M0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-110 DxTEST Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-8TEST_PIEVECTR/W0hSelects the defferent modes for PIEVECT RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Functional Mode.
Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation.

Reset type: SYSRSn

7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2TEST_M1R/W0hSelects the defferent modes for M1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on error.
Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation.

Reset type: SYSRSn

1-0TEST_M0R/W0hSelects the defferent modes for M0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on error.
Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation.

Reset type: SYSRSn

3.15.7.6 DxINIT Register (Offset = 12h) [Reset = 00000000h]

DxINIT is shown in Figure 3-97 and described in Table 3-111.

Return to the Summary Table.

Dedicated RAM Init Register

Figure 3-97 DxINIT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDINIT_PIEVECTRESERVEDRESERVEDINIT_M1INIT_M0
R-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 3-111 DxINIT Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4INIT_PIEVECTR-0/W1S0hRAM Initialization control for PIEVECT RAM:
0: None.
1: Start RAM Initialization.

Reset type: SYSRSn

3RESERVEDR-0/W1S0hReserved
2RESERVEDR-0/W1S0hReserved
1INIT_M1R-0/W1S0hRAM Initialization control for M1 RAM:
0: None.
1: Start RAM Initialization.

Reset type: SYSRSn

0INIT_M0R-0/W1S0hRAM Initialization control for M0 RAM:
0: None.
1: Start RAM Initialization.

Reset type: SYSRSn

3.15.7.7 DxINITDONE Register (Offset = 14h) [Reset = 00000000h]

DxINITDONE is shown in Figure 3-98 and described in Table 3-112.

Return to the Summary Table.

Dedicated RAM InitDone Status Register

Figure 3-98 DxINITDONE Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDINITDONE_PIEVECTRESERVEDRESERVEDINITDONE_M1INITDONE_M0
R-0hR-0hR-0hR-0hR-0hR-0h
Table 3-112 DxINITDONE Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4INITDONE_PIEVECTR0hRAM Initialization status for PIEVECT RAM:
0: RAM Initialization has completed.
1: RAM Initialization has completed.

Reset type: SYSRSn

3RESERVEDR0hReserved
2RESERVEDR0hReserved
1INITDONE_M1R0hRAM Initialization status for M1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization has completed.

Reset type: SYSRSn

0INITDONE_M0R0hRAM Initialization status for M0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.

Reset type: SYSRSn

3.15.7.8 DxRAMTEST_LOCK Register (Offset = 16h) [Reset = 00000000h]

DxRAMTEST_LOCK is shown in Figure 3-99 and described in Table 3-113.

Return to the Summary Table.

Lock register to Dx RAM TEST registers

Figure 3-99 DxRAMTEST_LOCK Register
3130292827262524
KEY
R-0/W-0h
2322212019181716
KEY
R-0/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPIEVECTRESERVEDRESERVEDM1M0
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-113 DxRAMTEST_LOCK Register Field Descriptions
BitFieldTypeResetDescription
31-16KEYR-0/W0hA value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed,

Reset type: SYSRSn

15-5RESERVEDR0hReserved
4PIEVECTR/W0h0: Allows writes to DxTEST.TEST_PIEVECT field.
1: Blocks writes to DxTEST.TEST_PIEVECT field

Reset type: SYSRSn

3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1M1R/W0h0: Allows writes to DxTEST.TEST_M1 field.
1: Blocks writes to DxTEST.TEST_M1 field

Reset type: SYSRSn

0M0R/W0h0: Allows writes to DxTEST.TEST_M0 field.
1: Blocks writes to DxTEST.TEST_M0 field

Reset type: SYSRSn

3.15.7.9 LSxLOCK Register (Offset = 20h) [Reset = 00000000h]

LSxLOCK is shown in Figure 3-100 and described in Table 3-114.

Return to the Summary Table.

Local Shared RAM Config Lock Register

Figure 3-100 LSxLOCK Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDLOCK_LS1LOCK_LS0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-114 LSxLOCK Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8RESERVEDR0hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1LOCK_LS1R/W0hLocks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS1 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.

Reset type: SYSRSn

0LOCK_LS0R/W0hLocks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS0 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.

Reset type: SYSRSn

3.15.7.10 LSxCOMMIT Register (Offset = 22h) [Reset = 00000000h]

LSxCOMMIT is shown in Figure 3-101 and described in Table 3-115.

Return to the Summary Table.

Local Shared RAM Config Lock Commit Register

Figure 3-101 LSxCOMMIT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCOMMIT_LS1COMMIT_LS0
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-115 LSxCOMMIT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8RESERVEDR0hReserved
7RESERVEDR/WSonce0hReserved
6RESERVEDR/WSonce0hReserved
5RESERVEDR/WSonce0hReserved
4RESERVEDR/WSonce0hReserved
3RESERVEDR/WSonce0hReserved
2RESERVEDR/WSonce0hReserved
1COMMIT_LS1R/WSonce0hPermanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS1 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently blocked.

Reset type: SYSRSn

0COMMIT_LS0R/WSonce0hPermanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS0 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently blocked.

Reset type: SYSRSn

3.15.7.11 LSxACCPROT0 Register (Offset = 28h) [Reset = 00000000h]

LSxACCPROT0 is shown in Figure 3-102 and described in Table 3-116.

Return to the Summary Table.

Local Shared RAM Config Register 0

Figure 3-102 LSxACCPROT0 Register
3130292827262524
RESERVEDRESERVEDRESERVED
R-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R-0hR/W-0hR/W-0h
15141312111098
RESERVEDCPUWRPROT_LS1FETCHPROT_LS1
R-0hR/W-0hR/W-0h
76543210
RESERVEDCPUWRPROT_LS0FETCHPROT_LS0
R-0hR/W-0hR/W-0h
Table 3-116 LSxACCPROT0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23-18RESERVEDR0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15-10RESERVEDR0hReserved
9CPUWRPROT_LS1R/W0hCPU WR Protection For LS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.

Reset type: SYSRSn

8FETCHPROT_LS1R/W0hFetch Protection For LS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.

Reset type: SYSRSn

7-2RESERVEDR0hReserved
1CPUWRPROT_LS0R/W0hCPU WR Protection For LS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.

Reset type: SYSRSn

0FETCHPROT_LS0R/W0hFetch Protection For LS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.

Reset type: SYSRSn

3.15.7.12 LSxTEST Register (Offset = 30h) [Reset = 00000000h]

LSxTEST is shown in Figure 3-103 and described in Table 3-117.

Return to the Summary Table.

Local Shared RAM TEST Register

Figure 3-103 LSxTEST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDTEST_LS1TEST_LS0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-117 LSxTEST Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2TEST_LS1R/W0hSelects the defferent modes for LS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on error.
Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation.

Reset type: SYSRSn

1-0TEST_LS0R/W0hSelects the defferent modes for LS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on error.
Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation.

Reset type: SYSRSn

3.15.7.13 LSxINIT Register (Offset = 32h) [Reset = 00000000h]

LSxINIT is shown in Figure 3-104 and described in Table 3-118.

Return to the Summary Table.

Local Shared RAM Init Register

Figure 3-104 LSxINIT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDINIT_LS1INIT_LS0
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 3-118 LSxINIT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8RESERVEDR0hReserved
7RESERVEDR-0/W1S0hReserved
6RESERVEDR-0/W1S0hReserved
5RESERVEDR-0/W1S0hReserved
4RESERVEDR-0/W1S0hReserved
3RESERVEDR-0/W1S0hReserved
2RESERVEDR-0/W1S0hReserved
1INIT_LS1R-0/W1S0hRAM Initialization control for LS1 RAM:
0: None.
1: Start RAM Initialization.

Reset type: SYSRSn

0INIT_LS0R-0/W1S0hRAM Initialization control for LS0 RAM:
0: None.
1: Start RAM Initialization.

Reset type: SYSRSn

3.15.7.14 LSxINITDONE Register (Offset = 34h) [Reset = 00000000h]

LSxINITDONE is shown in Figure 3-105 and described in Table 3-119.

Return to the Summary Table.

Local Shared RAM InitDone Status Register

Figure 3-105 LSxINITDONE Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDINITDONE_LS1INITDONE_LS0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 3-119 LSxINITDONE Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8RESERVEDR0hReserved
7RESERVEDR0hReserved
6RESERVEDR0hReserved
5RESERVEDR0hReserved
4RESERVEDR0hReserved
3RESERVEDR0hReserved
2RESERVEDR0hReserved
1INITDONE_LS1R0hRAM Initialization status for LS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.

Reset type: SYSRSn

0INITDONE_LS0R0hRAM Initialization status for LS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.

Reset type: SYSRSn

3.15.7.15 LSxRAMTEST_LOCK Register (Offset = 36h) [Reset = 00000000h]

LSxRAMTEST_LOCK is shown in Figure 3-106 and described in Table 3-120.

Return to the Summary Table.

Lock register to LSx RAM TEST registers

Figure 3-106 LSxRAMTEST_LOCK Register
31302928272625242322212019181716
KEY
R-0/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDLS1LS0
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-120 LSxRAMTEST_LOCK Register Field Descriptions
BitFieldTypeResetDescription
31-16KEYR-0/W0hA value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed,

Reset type: SYSRSn

15-8RESERVEDR0hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1LS1R/W0h0: Allows writes to LSxTEST.TEST_LS1 field.
1: Blocks writes to LSxTEST.TEST_LS1 field.

Reset type: SYSRSn

0LS0R/W0h0: Allows writes to LSxTEST.TEST_LS0 field.
1: Blocks writes to LSxTEST.TEST_LS0 field.

Reset type: SYSRSn

3.15.7.16 ROM_LOCK Register (Offset = A0h) [Reset = 00000000h]

ROM_LOCK is shown in Figure 3-107 and described in Table 3-121.

Return to the Summary Table.

ROM Config Lock Register

Figure 3-107 ROM_LOCK Register
3130292827262524
KEY
R-0/W-0h
2322212019181716
KEY
R-0/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDLOCK_BOOTROM
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-121 ROM_LOCK Register Field Descriptions
BitFieldTypeResetDescription
31-16KEYR-0/W0hA value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed,

Reset type: SYSRSn

15-4RESERVEDR0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0LOCK_BOOTROMR/W0hLocks write access to test control fields (TEST and FORCE_ERROR) of BOOTROM
0: Write access allowed
1: Write access blocked

Reset type: SYSRSn

3.15.7.17 ROM_TEST Register (Offset = A2h) [Reset = 00000000h]

ROM_TEST is shown in Figure 3-108 and described in Table 3-122.

Return to the Summary Table.

ROM TEST Register

Figure 3-108 ROM_TEST Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRESERVEDRESERVEDTEST_BOOTROM
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-122 ROM_TEST Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2RESERVEDR/W0hReserved
1-0TEST_BOOTROMR/W0hSelects the different modes for BOOTROM:
00: Functional Mode.
01: same as '00' but Parity check on data read is disabled (for debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as '00' but NMI is not generated on errors, used for diagnostics. (for diagnostics)

Reset type: SYSRSn

3.15.7.18 ROM_FORCE_ERROR Register (Offset = A4h) [Reset = 00000000h]

ROM_FORCE_ERROR is shown in Figure 3-109 and described in Table 3-123.

Return to the Summary Table.

ROM Force Error register

Figure 3-109 ROM_FORCE_ERROR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDFORCE_BOOTROM_ERROR
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-123 ROM_FORCE_ERROR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-4RESERVEDR0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0FORCE_BOOTROM_ERRORR/W0hForce parity error by feeding inverted Parity bit to Parity checking logic.

Reset type: SYSRSn