-
J7200 DRA821 Processor Texas Instruments Families of Products
- 1
- Read This First
-
1 Introduction
- 1.1 Device Overview
- 1.2 Device Block Diagram
- 1.3
Device Main Domain
- 1.3.1 Arm Cortex-A72 Subsystem
- 1.3.2 Arm Cortex-R5F Processor
- 1.3.3 Navigator Subsystem
- 1.3.4 Region-based Address Translation Module
- 1.3.5 Multicore Shared Memory Controller
- 1.3.6 DDR Subsystem
- 1.3.7 General Purpose Input/Output Interface
- 1.3.8 Inter-Integrated Circuit Interface
- 1.3.9 Improved Inter-Integrated Circuit Interface
- 1.3.10 Multi-channel Serial Peripheral Interface
- 1.3.11 Universal Asynchronous Receiver/Transmitter
- 1.3.12 Gigabit Ethernet Switch
- 1.3.13 Peripheral Component Interconnect Express Subsystem
- 1.3.14 Universal Serial Bus (USB) Subsystem
- 1.3.15 SerDes
- 1.3.16 General Purpose Memory Controller with Error Location Module
- 1.3.17 Multimedia Card/Secure Digital Interface
- 1.3.18 Enhanced Capture Module
- 1.3.19 Enhanced Pulse-Width Modulation Module
- 1.3.20 Enhanced Quadrature Encoder Pulse Module
- 1.3.21 Controller Area Network
- 1.3.22 Audio Tracking Logic
- 1.3.23 Multi-channel Audio Serial Port
- 1.3.24 Timers
- 1.3.25 Internal Diagnostics Modules
- 1.4
Device MCU Domain
- 1.4.1 MCU Arm Cortex-R5F Processor
- 1.4.2 MCU Region-based Address Translation Module
- 1.4.3 MCU Navigator Subsystem
- 1.4.4 MCU Analog-to-Digital Converter
- 1.4.5 MCU Inter-Integrated Circuit Interface
- 1.4.6 MCU Improved Inter-Integrated Circuit Interface
- 1.4.7 MCU Multi-channel Serial Peripheral Interface
- 1.4.8 MCU Universal Asynchronous Receiver/Transmitter
- 1.4.9 MCU Gigabit Ethernet Switch
- 1.4.10 MCU Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
- 1.4.11 MCU Controller Area Network
- 1.4.12 MCU Timers
- 1.4.13 MCU Internal Diagnostics Modules
- 1.5 Device WKUP Domain
- 1.6 Device Identification
- 2 Memory Map
-
3 System Interconnect
- 3.1 System Interconnect Overview
- 3.2 System Interconnect Integration
- 3.3
System Interconnect Functional Description
- 3.3.1 Master-Slave Connections
- 3.3.2 Quality of Service (QoS)
- 3.3.3 Route ID
- 3.3.4 Initiator-Side Security Controls and Firewalls
- 3.3.5 Null Error Reporting
- 3.3.6
VBUSM_TIMEOUT_GASKET
(MCU_TIMEOUT_64B2)
- 3.3.6.1 Overview and Feature List
- 3.3.6.2
Functional Description
- 3.3.6.2.1
Functional Operation
- 3.3.6.2.1.1 Overview
- 3.3.6.2.1.2 FIFOs
- 3.3.6.2.1.3 ID Allocator
- 3.3.6.2.1.4 Timer
- 3.3.6.2.1.5 Timeout Queue
- 3.3.6.2.1.6 Write Scoreboard
- 3.3.6.2.1.7 Read Scoreboard
- 3.3.6.2.1.8 Flush Mode
- 3.3.6.2.1.9 Flushing
- 3.3.6.2.1.10 Timeout Error Reporting
- 3.3.6.2.1.11 Command Timeout Error Reporting
- 3.3.6.2.1.12 Unexpected Response Reporting
- 3.3.6.2.1.13 Latency and Stalls
- 3.3.6.2.1.14 Bypass
- 3.3.6.2.1.15 Safety
- 3.3.6.2.1
Functional Operation
- 3.3.6.3 Interrupt Conditions
- 3.3.6.4
Memory Map
- 3.3.6.4.1 Revision Register (Base Address + 0x00)
- 3.3.6.4.2 Configuration Register (Base Address + 0x04)
- 3.3.6.4.3 Info Register (Base Address + 0x08)
- 3.3.6.4.4 Enable Register (Base Address + 0x0C)
- 3.3.6.4.5 Flush Register (Base Address + 0x10)
- 3.3.6.4.6 Timeout Value Register (Base Address + 0x14)
- 3.3.6.4.7 Timer Register (Base Address + 0x18)
- 3.3.6.4.8 Error Interrupt Raw Status/Set Register (Base Address + 0x20)
- 3.3.6.4.9 Error Interrupt Enabled Status/Clear Register (Base Address + 0x24)
- 3.3.6.4.10 Error Interrupt Mask Set Register (Base Address + 0x28)
- 3.3.6.4.11 Error Interrupt Mask Clear Register (Base Address + 0x2C)
- 3.3.6.4.12 Timeout Error Info Register (Base Address + 0x30)
- 3.3.6.4.13 Unexpected Response Info Register (Base Address + 0x34)
- 3.3.6.4.14 Error Transaction Valid/Dir/RouteID Register (Base Address + 0x38)
- 3.3.6.4.15 Error Transaction Tag/CommandID Register (Base Address + 0x3C)
- 3.3.6.4.16 Error Transaction Bytecnt Register (Base Address + 0x40)
- 3.3.6.4.17 Error Transaction Upper Address Register (Base Address + 0x44)
- 3.3.6.4.18 Error Transaction Lower Address Register (Base Address + 0x48)
- 3.3.6.5 Integration Overview
- 3.3.6.6 I/O Description
- 3.3.6.7 User’s Guide
- 3.3.7 Timeout Gasket (TOG)
- 3.4 System Interconnect Registers
-
4 Initialization
- 4.1 Initialization Overview
- 4.2 Boot Process
- 4.3
Boot Mode Pins
- 4.3.1 MCU_BOOTMODE Pin Mapping
- 4.3.2 BOOTMODE Pin Mapping
- 4.3.3 No-boot/Dev-boot Configuration
- 4.3.4 Hyperflash Boot Device Configuration
- 4.3.5 OSPI Boot Device Configuration
- 4.3.6 QSPI Boot Device Configuration
- 4.3.7 SPI Boot Device Configuration
- 4.3.8 xSPI Boot Device Configuration
- 4.3.9 I2C Boot Device Configuration
- 4.3.10 MMC/SD Card Boot Device Configuration
- 4.3.11 eMMC Boot Device Configuration
- 4.3.12 Ethernet Boot Device Configuration
- 4.3.13 USB Boot Device Configuration
- 4.3.14 PCIe Boot Device Configuration
- 4.3.15 UART Boot Device Configuration
- 4.3.16 PLL Configuration
- 4.4
Boot Parameter Tables
- 4.4.1 Common Header
- 4.4.2 PLL Setup
- 4.4.3 PCIe Boot Parameter Table
- 4.4.4 I2C Boot Parameter Table
- 4.4.5 OSPI/QSPI/SPI Boot Parameter Table
- 4.4.6 Ethernet Boot Parameter Table
- 4.4.7 USB Boot Parameter Table
- 4.4.8 MMCSD Boot Parameter Table
- 4.4.9 UART Boot Parameter Table
- 4.4.10 Hyperflash Boot Parameter Table
- 4.5 Boot Image Format
- 4.6
Boot Modes
- 4.6.1 I2C Bootloader Operation
- 4.6.2 SPI Bootloader Operation
- 4.6.3 QSPI Bootloader Operation
- 4.6.4 OSPI Bootloader Operation
- 4.6.5 PCIe Bootloader Operation
- 4.6.6 Ethernet Bootloader Operation
- 4.6.7 USB Bootloader Operation
- 4.6.8 MMCSD Bootloader Operation
- 4.6.9 UART Bootloader Operation
- 4.7 Boot Memory Maps
-
5 Device Configuration
- 5.1
Control Module (CTRL_MMR)
- 5.1.1
WKUP_CTRL_MMR0
- 5.1.1.1 WKUP_CTRL_MMR0 Overview
- 5.1.1.2 WKUP_CTRL_MMR0 Integration
- 5.1.1.3
WKUP_CTRL_MMR0 Functional Description
- 5.1.1.3.1
Description for WKUP_CTRL_MMR0 Register Types
- 5.1.1.3.1.1 Pad Configuration Registers
- 5.1.1.3.1.2 Kick Protection Registers
- 5.1.1.3.1.3 WKUP_CTRL_MMR0 Module Interrupts
- 5.1.1.3.1.4 Clock Selection Registers
- 5.1.1.3.1.5 Device Feature Registers
- 5.1.1.3.1.6 POK Module Registers
- 5.1.1.3.1.7 Power and Reset Related Registers
- 5.1.1.3.1.8 PRG Related Registers
- 5.1.1.3.1.9 Voltage Glitch Detect Control and Status Registers
- 5.1.1.3.1.10 I/O Debounce Control Registers
- 5.1.1.3.1
Description for WKUP_CTRL_MMR0 Register Types
- 5.1.1.4 WKUP_CTRL_MMR0 Registers
- 5.1.2 MCU_CTRL_MMR0
- 5.1.3
CTRL_MMR0
- 5.1.3.1 CTRL_MMR0 Overview
- 5.1.3.2 CTRL_MMR0 Integration
- 5.1.3.3
CTRL_MMR0 Functional Description
- 5.1.3.3.1
Description for CTRL_MMR0 Register Types
- 5.1.3.3.1.1 Pad Configuration Registers
- 5.1.3.3.1.2 Kick Protection Registers
- 5.1.3.3.1.3 CTRL_MMR0 Module Interrupts
- 5.1.3.3.1.4 Inter-processor Communication Registers
- 5.1.3.3.1.5 Timer I/O Muxing Control Registers
- 5.1.3.3.1.6 EHRPWM/EQEP Control and Status Registers
- 5.1.3.3.1.7 Clock Muxing and Division Registers
- 5.1.3.3.1.8 Ethernet Port Operation Control Registers
- 5.1.3.3.1.9 SERDES Lane Function Control Registers
- 5.1.3.3.1.10 DDRSS Dynamic Frequency Change Registers
- 5.1.3.3.1
Description for CTRL_MMR0 Register Types
- 5.1.3.4 CTRL_MMR0 Registers
- 5.1.3.5 SEC_MMR0_DBG_CTRL Registers
- 5.1.3.6 SEC_MMR0_BOOT_CTRL Registers
- 5.1.1
WKUP_CTRL_MMR0
- 5.2
Power
- 5.2.1 Power Management Overview
- 5.2.2
Power Management Subsystems
- 5.2.2.1 Power Subsystems Overview
- 5.2.2.2
Power System Modules
- 5.2.2.2.1 Power OK (POK) Modules
- 5.2.2.2.2 Power on Reset (POR) Module
- 5.2.2.2.3 PoR/Reset Generator (PRG_PP) Modules
- 5.2.2.2.4 Power Glitch Detect (PGD) Modules
- 5.2.2.2.5
Voltage and Thermal Manager (VTM)
- 5.2.2.2.5.1 VTM Overview
- 5.2.2.2.5.2 VTM Integration
- 5.2.2.2.5.3
VTM Functional Description
- 5.2.2.2.5.3.1 VTM Temperature Status and Thermal Management
- 5.2.2.2.5.3.2 VTM Temperature Driven Alerts and Interrupts
- 5.2.2.2.5.3.3 VTM VID Voltage Domains
- 5.2.2.2.5.3.4 VTM Clocking
- 5.2.2.2.5.3.5 VTM Retention Interface
- 5.2.2.2.5.3.6 VTM ECC Aggregator
- 5.2.2.2.5.3.7 VTM Programming Model
- 5.2.2.2.5.3.8 AVS-Class0
- 5.2.2.2.6 Distributed Power Clock and Reset Controller (DPCR)
- 5.2.2.3
Power Control Modules
- 5.2.2.3.1
Power Sleep Controller and Local Power Sleep Controllers
- 5.2.2.3.1.1 PSC Terminology
- 5.2.2.3.1.2 PSC Features
- 5.2.2.3.1.3 PSC: Device Power-Management Layout
- 5.2.2.3.1.4 PSC: Power Domain and Module States
- 5.2.2.3.1.5 PSC: Executing State Transitions
- 5.2.2.3.1.6 PSC: Emulation Support in the PSC
- 5.2.2.3.1.7 PSC: A72SS, MSMC, MCU Cortex-R5F, C71SS0, and C66SS Subsystem Power-Up and Power-Down Sequences
- 5.2.2.3.2 Integrated Power Management (DMSC)
- 5.2.2.3.1
Power Sleep Controller and Local Power Sleep Controllers
- 5.2.3 Device Power States
- 5.2.4 Dynamic Power Management
- 5.2.5 Thermal Management
- 5.2.6 Registers
- 5.3 Reset
- 5.4
Clocking
- 5.4.1 Overview
- 5.4.2 Clock Inputs
- 5.4.3 Clock Outputs
- 5.4.4 Device Oscillators
- 5.4.5
PLLs
- 5.4.5.1 WKUP and MCU Domains PLL Overview
- 5.4.5.2 MAIN Domain PLLs Overview
- 5.4.5.3 PLL Reference Clocks
- 5.4.5.4 Generic PLL Overview
- 5.4.5.5 PLLs Device-Specific Information
- 5.4.5.6 PLL and PLL Controller Connection
- 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
- 5.4.6 Registers
- 5.1
Control Module (CTRL_MMR)
-
6 Processors and Accelerators
- 6.1 Compute Cluster
- 6.2
Dual-A72 MPU
Subsystem
- 6.2.1 A72SS Overview
- 6.2.2 A72SS Integration
- 6.2.3
A72SS Functional Description
- 6.2.3.1 A72SS Block Diagram
- 6.2.3.2 A72SS A72 Cluster
- 6.2.3.3 A72SS Interfaces and Async Bridges
- 6.2.3.4 A72SS Interrupts
- 6.2.3.5 A72SS Power Management, Clocking and Reset
- 6.2.3.6 A72SS Debug Support
- 6.2.3.7 A72SS Timestamps
- 6.2.3.8 A72SS Watchdog
- 6.2.3.9 A72SS Internal Diagnostics
- 6.2.3.10 A72SS Cache Pre-Warming
- 6.2.3.11 A72SS Boot
- 6.2.3.12 A72SS IPC with Other CPUs
- 6.2.4 A72SS Registers
- 6.3
Dual-R5F MCU Subsystem
- 6.3.1 R5FSS Overview
- 6.3.2 R5FSS Integration
- 6.3.3
R5FSS Functional Description
- 6.3.3.1 R5FSS Block Diagram
- 6.3.3.2 R5FSS Cortex-R5F Core
- 6.3.3.3 R5FSS Interfaces
- 6.3.3.4 R5FSS Power, Clocking and Reset
- 6.3.3.5 R5FSS Lockstep Error Detection Logic
- 6.3.3.6 R5FSS Vectored Interrupt Manager (VIM)
- 6.3.3.7 R5FSS Region Address Translation (RAT)
- 6.3.3.8 R5FSS ECC Support
- 6.3.3.9 R5FSS Memory View
- 6.3.3.10 R5FSS Interrupts
- 6.3.3.11 R5FSS Debug and Trace
- 6.3.3.12 R5FSS Boot Options
- 6.3.3.13 R5FSS Core Memory ECC Events
- 6.3.4 R5FSS Registers
-
7 Interprocessor Communication
- 7.1
Mailbox
- 7.1.1 Mailbox Overview
- 7.1.2 Mailbox Integration
- 7.1.3 Mailbox Functional Description
- 7.1.4 Mailbox Programming Guide
- 7.2 Spinlock
- 7.1
Mailbox
-
8 Memory Controllers
- 8.1
Multicore Shared Memory Controller (MSMC)
- 8.1.1 MSMC Overview
- 8.1.2 MSMC Integration
- 8.1.3
MSMC Functional Description
- 8.1.3.1 MSMC Block Diagram
- 8.1.3.2 MSMC On-Chip Memory Banking
- 8.1.3.3 MSMC Snoop Filter and Data Cache
- 8.1.3.4 MSMC Access Protection Checks
- 8.1.3.5 MSMC Null Slave
- 8.1.3.6 MSMC Resource Arbitration
- 8.1.3.7 MSMC Error Detection and Correction
- 8.1.3.8 MSMC Interrupts
- 8.1.3.9 MSMC Memory Regions
- 8.1.3.10 MSMC Hardware Coherence
- 8.1.3.11 MSMC Quality-of-Service
- 8.1.3.12 MSMC Memory Regions Protection
- 8.1.3.13 MSMC Cache Tag View
- 8.1.4 MSMC Registers
- 8.2
DDR Subsystem (DDRSS)
- 8.2.1 DDRSS Overview
- 8.2.2 DDRSS Environment
- 8.2.3 DDRSS Integration
- 8.2.4
DDRSS Functional Description
- 8.2.4.1 DDRSS MSMC2DDR Bridge
- 8.2.4.2 DDRSS Interrupts
- 8.2.4.3 DDRSS Memory Regions
- 8.2.4.4 DDRSS ECC Support
- 8.2.4.5 DDRSS Dynamic Frequency Change Interface
- 8.2.4.6
DDR Controller Functional Description
- 8.2.4.6.1 DDR PHY Interface (DFI)
- 8.2.4.6.2 Command Queue
- 8.2.4.6.3 Low Power Control
- 8.2.4.6.4 Transaction Processing
- 8.2.4.6.5 BIST Engine
- 8.2.4.6.6 ECC Engine
- 8.2.4.6.7 Address Mapping
- 8.2.4.6.8 Paging Policy
- 8.2.4.6.9 DDR Controller Initialization
- 8.2.4.6.10 Programming LPDDR4 Memories
- 8.2.4.7
DDR PHY Functional Description
- 8.2.4.7.1 Data Slice
- 8.2.4.7.2 Address Slice
- 8.2.4.7.3 Address/Control Slice
- 8.2.4.7.4 Clock Slice
- 8.2.4.7.5 DDR PHY Initialization
- 8.2.4.7.6 DDR PHY Dynamic Frequency Scaling (DFS)
- 8.2.4.7.7 Chip Select and Frequency Based Register Settings
- 8.2.4.7.8 Low-Power Modes
- 8.2.4.7.9 Training Support
- 8.2.4.7.10 Data Bus Inversion (DBI)
- 8.2.4.7.11 I/O Pad Calibration
- 8.2.4.7.12 DQS Error
- 8.2.4.8 PI Functional Description
- 8.2.5 DDRSS Registers
- 8.3
Peripheral Virtualization Unit (PVU)
- 8.3.1 PVU Overview
- 8.3.2 PVU Integration
- 8.3.3
PVU Functional Description
- 8.3.3.1 Functional Operation Overview
- 8.3.3.2 PVU Channels
- 8.3.3.3 TLB
- 8.3.3.4 TLB Entry
- 8.3.3.5 TLB Selection
- 8.3.3.6 DMA Classes
- 8.3.3.7 General virtIDs
- 8.3.3.8 TLB Lookup
- 8.3.3.9 TLB Miss
- 8.3.3.10 Multiple Matching Entries
- 8.3.3.11 TLB Disable
- 8.3.3.12 TLB Chaining
- 8.3.3.13 TLB Permissions
- 8.3.3.14 Translation
- 8.3.3.15 Memory Attributes
- 8.3.3.16 Faulted Transactions
- 8.3.3.17 Non-Virtual Transactions
- 8.3.3.18 Allowed virtIDs
- 8.3.3.19 Software Control
- 8.3.3.20 Fault Logging
- 8.3.3.21 Alignment Restrictions
- 8.3.4 PVU Registers
- 8.4 Region-based Address Translation (RAT) Module
- 8.1
Multicore Shared Memory Controller (MSMC)
-
9 Interrupts
- 9.1 Interrupt Architecture
- 9.2 Interrupt Controllers
- 9.3 Interrupt Routers
- 9.4
Interrupt Sources
- 9.4.1 WKUP Domain Interrupt Maps
- 9.4.2 MCU Domain Interrupt Maps
- 9.4.3 MAIN Domain Interrupt Maps
-
10Data Movement Architecture (DMA)
- 10.1
DMA Architecture
- 10.1.1
Overview
- 10.1.1.1 Navigator Subsystem
- 10.1.1.2 Ring Accelerator (RA)
- 10.1.1.3 Proxy
- 10.1.1.4 Secure Proxy
- 10.1.1.5 Interrupt Aggregator (INTA)
- 10.1.1.6 Interrupt Router (IR)
- 10.1.1.7 Unified DMA – Third Party Channel Controller (UDMA-C)
- 10.1.1.8 Unified Transfer Controller (UTC)
- 10.1.1.9 Data Routing Unit (DRU)
- 10.1.1.10 Unified DMA – Peripheral Root Complex (UDMA-P)
- 10.1.1.11 Peripheral DMA (PDMA)
- 10.1.1.12 Embedded DMA
- 10.1.1.13 Definition of Terms
- 10.1.2
DMA Hardware/Software Interface
- 10.1.2.1 Data Buffers
- 10.1.2.2 Descriptors
- 10.1.2.3
Transfer Request Record
- 10.1.2.3.1 Overview
- 10.1.2.3.2 Addressing Algorithm
- 10.1.2.3.3 Transfer Request Formats
- 10.1.2.3.4
Flags Field Definition
- 10.1.2.3.4.1 Type: TR Type Field
- 10.1.2.3.4.2 STATIC: Static Field Definition
- 10.1.2.3.4.3 EVENT_SIZE: Event Generation Definition
- 10.1.2.3.4.4 TRIGGER INFO: TR Triggers
- 10.1.2.3.4.5 TRIGGERX_TYPE: Trigger Type
- 10.1.2.3.4.6 TRIGGERX: Trigger Selection
- 10.1.2.3.4.7 CMD ID: Command ID Field Definition
- 10.1.2.3.4.8 Configuration Specific Flags Definition
- 10.1.2.3.5
TR Address and Size Attributes
- 10.1.2.3.5.1 ICNT0
- 10.1.2.3.5.2 ICNT1
- 10.1.2.3.5.3 ADDR
- 10.1.2.3.5.4 DIM1
- 10.1.2.3.5.5 ICNT2
- 10.1.2.3.5.6 ICNT3
- 10.1.2.3.5.7 DIM2
- 10.1.2.3.5.8 DIM3
- 10.1.2.3.5.9 DDIM1
- 10.1.2.3.5.10 DADDR
- 10.1.2.3.5.11 DDIM2
- 10.1.2.3.5.12 DDIM3
- 10.1.2.3.5.13 DICNT0
- 10.1.2.3.5.14 DICNT1
- 10.1.2.3.5.15 DICNT2
- 10.1.2.3.5.16 DICNT3
- 10.1.2.3.6
FMTFLAGS
- 10.1.2.3.6.1 AMODE: Addressing Mode Definition
- 10.1.2.3.6.2 DIR: Addressing Mode Direction Definition
- 10.1.2.3.6.3 ELTYPE: Element Type Definition
- 10.1.2.3.6.4 DFMT: Data Formatting Algorithm Definition
- 10.1.2.3.6.5 SECTR: Secondary Transfer Request Definition
- 10.1.2.3.6.6 AMODE SPECIFIC: Addressing Mode Field
- 10.1.2.3.6.7 Cache Flags
- 10.1.2.4 Transfer Response Record
- 10.1.2.5
Queues
- 10.1.2.5.1
Queue Types
- 10.1.2.5.1.1 Transmit Queues (Pass By Reference)
- 10.1.2.5.1.2 Transmit Queues (Pass By Value)
- 10.1.2.5.1.3 Transmit Completion Queues (Pass By Reference)
- 10.1.2.5.1.4 Transmit Completion Queues (Pass By Value)
- 10.1.2.5.1.5 Receive Queues
- 10.1.2.5.1.6 Free Descriptor Queues
- 10.1.2.5.1.7 Free Descriptor/Buffer Queues
- 10.1.2.5.2 Ring Accelerator Queues Implementation
- 10.1.2.5.1
Queue Types
- 10.1.3
Operational Description
- 10.1.3.1 Resource Allocation
- 10.1.3.2 Ring Accelerator Operation
- 10.1.3.3 UDMA Internal Transmit Channel Setup (All Packet Types)
- 10.1.3.4 UDMA Internal Transmit Channel Teardown (All Packet Types)
- 10.1.3.5 UDMA External Transmit Channel Setup
- 10.1.3.6 UDMA Transmit External Channel Teardown
- 10.1.3.7 UDMA-P Transmit Channel Pause
- 10.1.3.8 UDMA-P Transmit Operation (Host Packet Type)
- 10.1.3.9 UDMA-P Transmit Operation (Monolithic Packet)
- 10.1.3.10 UDMA Transmit Operation (TR Packet)
- 10.1.3.11 UDMA Transmit Operation (Direct TR)
- 10.1.3.12 UDMA Transmit Error/Exception Handling
- 10.1.3.13 UDMA Receive Channel Setup (All Packet Types)
- 10.1.3.14 UDMA Receive Channel Teardown
- 10.1.3.15 UDMA-P Receive Channel Pause
- 10.1.3.16 UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
- 10.1.3.17 UDMA-P Receive FlowID Firewall Operation
- 10.1.3.18 UDMA-P Receive Operation (Host Packet)
- 10.1.3.19 UDMA-P Receive Operation (Monolithic Packet)
- 10.1.3.20 UDMA Receive Operation (TR Packet)
- 10.1.3.21 UDMA Receive Operation (Direct TR)
- 10.1.3.22 UDMA Receive Error/Exception Handling
- 10.1.3.23 UTC Operation
- 10.1.3.24 UTC Receive Error/Exception Handling
- 10.1.1
Overview
- 10.2
Navigator Subsystem (NAVSS)
- 10.2.1 Main Navigator Subsystem (NAVSS)
- 10.2.2
MCU Navigator Subsystem (MCU NAVSS)
- 10.2.2.1 MCU NAVSS Overview
- 10.2.2.2
MCU NAVSS Integration
- 10.2.2.2.1 MCU NAVSS Interrupt Router Configuration
- 10.2.2.2.2 MCU NAVSS UDMASS Interrupt Aggregator Configuration
- 10.2.2.2.3 MCU NAVSS UDMA Configuration
- 10.2.2.2.4 MCU NAVSS Ring Accelerator Configuration
- 10.2.2.2.5 MCU NAVSS Proxy Configuration
- 10.2.2.2.6 MCU NAVSS Secure Proxy Configuration
- 10.2.2.2.7 Global Event Map
- 10.2.2.2.8 PSI-L System Thread Map (All NAVSS)
- 10.2.2.2.9 MCU NAVSS VBUSM Route ID Table
- 10.2.2.2.10 1008
- 10.2.2.3 MCU NAVSS Functional Description
- 10.2.2.4 MCU NAVSS Top-Level Registers
- 10.2.3
Unified DMA Controller (UDMA)
- 10.2.3.1 UDMA Overview
- 10.2.3.2 UDMA Integration
- 10.2.3.3
UDMA Functional Description
- 10.2.3.3.1 Block Diagram
- 10.2.3.3.2 General Functionality
- 10.2.3.3.3 Packet Oriented Transmit Operation
- 10.2.3.3.4 Packet Oriented Receive Operation
- 10.2.3.3.5 Third Party Mode Operation
- 10.2.3.4 UDMA Registers
- 10.2.4
Ring Accelerator (RINGACC)
- 10.2.4.1 RINGACC Overview
- 10.2.4.2 RINGACC Integration
- 10.2.4.3
RINGACC Functional Description
- 10.2.4.3.1
Block Diagram
- 10.2.4.3.1.1 Configuration Registers
- 10.2.4.3.1.2 Source Command FIFO
- 10.2.4.3.1.3 Source Write Data FIFO
- 10.2.4.3.1.4 Source Read Data FIFO
- 10.2.4.3.1.5 Source Write Status FIFO
- 10.2.4.3.1.6 Main State Machine
- 10.2.4.3.1.7 Destination Command FIFO
- 10.2.4.3.1.8 Destination Write Data FIFO
- 10.2.4.3.1.9 Destination Read Data FIFO
- 10.2.4.3.1.10 Destination Write Status FIFO
- 10.2.4.3.2
RINGACC Functional Operation
- 10.2.4.3.2.1 Queue Modes
- 10.2.4.3.2.2 VBUSM Slave Ring Operations
- 10.2.4.3.2.3 VBUSM Master Interface Command ID Selection
- 10.2.4.3.2.4 Ring Push Operation (VBUSM Write to Source Interface)
- 10.2.4.3.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
- 10.2.4.3.2.6 Host Doorbell Access
- 10.2.4.3.2.7 Queue Push Operation (VBUSM Write to Source Interface)
- 10.2.4.3.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
- 10.2.4.3.2.9 Mismatched Element Size Handling
- 10.2.4.3.3 Events
- 10.2.4.3.4 Bus Error Handling
- 10.2.4.3.5 Monitors
- 10.2.4.3.1
Block Diagram
- 10.2.4.4 RINGACC Registers
- 10.2.5
Proxy
- 10.2.5.1 Proxy Overview
- 10.2.5.2 Proxy Integration
- 10.2.5.3 Proxy Functional Description
- 10.2.5.4 Proxy Registers
- 10.2.6
Secure Proxy
- 10.2.6.1 Secure Proxy Overview
- 10.2.6.2 Secure Proxy Integration
- 10.2.6.3
Secure Proxy Functional Description
- 10.2.6.3.1 Targets
- 10.2.6.3.2 Buffers
- 10.2.6.3.3 Proxy Thread Sizes
- 10.2.6.3.4 Proxy Thread Interleaving
- 10.2.6.3.5 Proxy States
- 10.2.6.3.6 Proxy Host Access
- 10.2.6.3.7 Permission Inheritance
- 10.2.6.3.8 Resource Association
- 10.2.6.3.9 Direction
- 10.2.6.3.10 Threshold Events
- 10.2.6.3.11 Error Events
- 10.2.6.3.12 Bus Errors and Credits
- 10.2.6.3.13 Debug
- 10.2.6.4 Secure Proxy Registers
- 10.2.7
Interrupt Aggregator (INTR_AGGR)
- 10.2.7.1 INTR_AGGR Overview
- 10.2.7.2 INTR_AGGR Integration
- 10.2.7.3
INTR_AGGR Functional Description
- 10.2.7.3.1 Submodule Descriptions
- 10.2.7.3.2
General Functionality
- 10.2.7.3.2.1 Event to Interrupt Bit Steering
- 10.2.7.3.2.2 Interrupt Status
- 10.2.7.3.2.3 Interrupt Masked Status
- 10.2.7.3.2.4 Enabling/Disabling Individual Interrupt Source Bits
- 10.2.7.3.2.5 Interrupt Output Generation
- 10.2.7.3.2.6 Global Event Counting
- 10.2.7.3.2.7 Local Event to Global Event Conversion
- 10.2.7.3.2.8 Global Event Multicast
- 10.2.7.4
INTR_AGGR Registers
- 10.2.7.4.1 MODSS_INTA_CFG Registers
- 10.2.7.4.2 MODSS_INTA_CFG_IMAP Registers
- 10.2.7.4.3 MODSS_INTA_CFG_INTR Registers
- 10.2.7.4.4 UDMASS_INTA0_CFG Registers
- 10.2.7.4.5 UDMASS_INTA0_CFG_INTR Registers
- 10.2.7.4.6 UDMASS_INTA0_CFG_IMAP Registers
- 10.2.7.4.7 UDMASS_INTA0_CFG_L2G Registers
- 10.2.7.4.8 UDMASS_INTA0_CFG_MCAST Registers
- 10.2.7.4.9 UDMASS_INTA0_CFG_GCNTCFG Registers
- 10.2.7.4.10 UDMASS_INTA0_CFG_GCNTRTI Registers
- 10.2.8 Packet Streaming Interface Link (PSI-L)
- 10.2.9 PSIL Subsystem (PSILSS)
- 10.2.10
NAVSS North Bridge (NB)
- 10.2.10.1 NB Overview
- 10.2.10.2
NB Functional Description
- 10.2.10.2.1 VBUSM Slave Interfaces
- 10.2.10.2.2 VBUSM Master Interface
- 10.2.10.2.3 VBUSM.C Interfaces
- 10.2.10.2.4 Source M2M Bridges
- 10.2.10.2.5 Destination M2M Bridge
- 10.2.10.2.6 M2C Bridge
- 10.2.10.2.7 Memory Attribute Tables
- 10.2.10.2.8 Outstanding Read Data Limiter
- 10.2.10.2.9 Ordering
- 10.2.10.2.10 Quality of Service
- 10.2.10.2.11 IDLE Behavior
- 10.2.10.2.12 Clock Power Management
- 10.2.10.3 NB Registers
- 10.3
Peripheral DMA (PDMA)
- 10.3.1
PDMA Controller
- 10.3.1.1
PDMA Overview
- 10.3.1.1.1
PDMA Features
- 10.3.1.1.1.1 MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
- 10.3.1.1.1.2 MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
- 10.3.1.1.1.3 MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
- 10.3.1.1.1.4 MCU_PDMA3 (MCU_PDMA_ADC) Features
- 10.3.1.1.1.5 PDMA2 (PDMA_DEBUG_CCMCU) Features
- 10.3.1.1.1.6 PDMA5 (PDMA_MCAN) Features
- 10.3.1.1.1.7 PDMA6 (PDMA_MCASP_G0) Features
- 10.3.1.1.1.8 PDMA9 (PDMA_SPI_G0) Features
- 10.3.1.1.1.9 PDMA10 (PDMA_SPI_G1) Features
- 10.3.1.1.1.10 PDMA13 (PDMA_USART_G0) Features
- 10.3.1.1.1.11 PDMA14 (PDMA_USART_G1) Features
- 10.3.1.1.1.12 PDMA15 (PDMA_USART_G2) Features
- 10.3.1.1.1
PDMA Features
- 10.3.1.2 PDMA Integration
- 10.3.1.3
PDMA Functional Description
- 10.3.1.3.1 PDMA Functional Blocks
- 10.3.1.3.2 PDMA General Functionality
- 10.3.1.3.3 PDMA Events and Flow Control
- 10.3.1.3.4 PDMA Transmit Operation
- 10.3.1.3.5 PDMA Receive Operation
- 10.3.1.3.6 PDMA ECC Support
- 10.3.1.4 PDMA Registers
- 10.3.1.1
PDMA Overview
- 10.3.2 PDMA Sources
- 10.3.1
PDMA Controller
- 10.1
DMA Architecture
-
11Time Sync
- 11.1
Time Sync Module (CPTS)
- 11.1.1 CPTS Overview
- 11.1.2 CPTS Integration
- 11.1.3
CPTS Functional Description
- 11.1.3.1 CPTS Architecture
- 11.1.3.2 CPTS Initialization
- 11.1.3.3 32-bit Time Stamp Value
- 11.1.3.4 64-bit Time Stamp Value
- 11.1.3.5 Event FIFO
- 11.1.3.6 Timestamp Compare Output
- 11.1.3.7 Timestamp Sync Output
- 11.1.3.8 Timestamp GENF Output
- 11.1.3.9 Time Sync Events
- 11.1.3.10 Timestamp Compare Event
- 11.1.3.11 CPTS Interrupt Handling
- 11.1.4 CPTS Registers
- 11.2 Timer Manager
- 11.3 Time Sync and Compare Events
- 11.1
Time Sync Module (CPTS)
-
12Peripherals
- 12.1
General Connectivity Peripherals
- 12.1.1
Analog-to-Digital Converter (ADC)
- 12.1.1.1 ADC Overview
- 12.1.1.2 ADC Environment
- 12.1.1.3 ADC Integration
- 12.1.1.4
ADC Functional Description
- 12.1.1.4.1 ADC FSM Sequencer Functional Description
- 12.1.1.4.2 ADC AFE Functional Description
- 12.1.1.4.3 ADC FIFOs and DMA
- 12.1.1.4.4 ADC Error Correcting Code (ECC)
- 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
- 12.1.1.5 ADC Programming Guide
- 12.1.1.6 ADC Registers
- 12.1.2
General-Purpose Interface (GPIO)
- 12.1.2.1 GPIO Overview
- 12.1.2.2 GPIO Environment
- 12.1.2.3 GPIO Integration
- 12.1.2.4 GPIO Functional Description
- 12.1.2.5 GPIO Programming Guide
- 12.1.2.6 GPIO Registers
- 12.1.3
Inter-Integrated Circuit (I2C) Interface
- 12.1.3.1 I2C Overview
- 12.1.3.2
I2C Environment
- 12.1.3.2.1 I2C Typical Application
- 12.1.3.2.2
I2C Typical Connection Protocol and Data Format
- 12.1.3.2.2.1 I2C Serial Data Format
- 12.1.3.2.2.2 I2C Data Validity
- 12.1.3.2.2.3 I2C Start and Stop Conditions
- 12.1.3.2.2.4 I2C Addressing
- 12.1.3.2.2.5 I2C Controller Transmitter
- 12.1.3.2.2.6 I2C Controller Receiver
- 12.1.3.2.2.7 I2C Target Transmitter
- 12.1.3.2.2.8 I2C Target Receiver
- 12.1.3.2.2.9 I2C Bus Arbitration
- 12.1.3.2.2.10 I2C Clock Generation and Synchronization
- 12.1.3.3 I2C Integration
- 12.1.3.4 I2C Functional Description
- 12.1.3.5 I2C Programming Guide
- 12.1.3.6 I2C Registers
- 12.1.4
Improved Inter-Integrated Circuit (I3C) Interface
- 12.1.4.1 I3C Overview
- 12.1.4.2 I3C Environment
- 12.1.4.3 I3C Integration
- 12.1.4.4
I3C Functional Description
- 12.1.4.4.1 I3C Block Diagram
- 12.1.4.4.2 I3C Clock Configuration
- 12.1.4.4.3 I3C Interrupt Requests
- 12.1.4.4.4 I3C Power Configuration
- 12.1.4.4.5 I3C Dynamic Address Management
- 12.1.4.4.6 I3C Retaining Registers Space
- 12.1.4.4.7 I3C Dynamic Address Assignment Procedure
- 12.1.4.4.8 I3C Sending CCC Messages
- 12.1.4.4.9 I3C In-Band Interrupt
- 12.1.4.4.10 I3C Hot-Join Request
- 12.1.4.4.11 I3C Immediate Commands
- 12.1.4.4.12 I3C Host Commands
- 12.1.4.4.13 I3C Sending Private Data in SDR Messages
- 12.1.4.5
I3C Programming Guide
- 12.1.4.5.1 I3C Power-On Programming Model
- 12.1.4.5.2 I3C Static Devices Programming
- 12.1.4.5.3 I3C DAA Procedure Initiation
- 12.1.4.5.4 I3C SDR Write Message Programming Model
- 12.1.4.5.5 I3C SDR Read Message Programming Model
- 12.1.4.5.6 I3C DDR Write Message Programming Model
- 12.1.4.5.7 I3C DDR Read Message Programming Model
- 12.1.4.6 I3C Registers
- 12.1.5
Multichannel Serial Peripheral Interface (MCSPI)
- 12.1.5.1 MCSPI Overview
- 12.1.5.2 MCSPI Environment
- 12.1.5.3 MCSPI Integration
- 12.1.5.4
MCSPI Functional Description
- 12.1.5.4.1 SPI Block Diagram
- 12.1.5.4.2 MCSPI Reset
- 12.1.5.4.3
MCSPI Controller Mode
- 12.1.5.4.3.1 Controller Mode Features
- 12.1.5.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
- 12.1.5.4.3.3 Controller Transmit-Only Mode (Half Duplex)
- 12.1.5.4.3.4 Controller Receive-Only Mode (Half Duplex)
- 12.1.5.4.3.5 Single-Channel Controller Mode
- 12.1.5.4.3.6 Start-Bit Mode
- 12.1.5.4.3.7 Chip-Select Timing Control
- 12.1.5.4.3.8 Programmable MCSPI Clock (SPICLK)
- 12.1.5.4.4 MCSPI Peripheral Mode
- 12.1.5.4.5 MCSPI 3-Pin or 4-Pin Mode
- 12.1.5.4.6 MCSPI FIFO Buffer Management
- 12.1.5.4.7 MCSPI Interrupts
- 12.1.5.4.8 MCSPI DMA Requests
- 12.1.5.4.9 MCSPI Power Saving Management
- 12.1.5.5
MCSPI Programming Guide
- 12.1.5.5.1 MCSPI Global Initialization
- 12.1.5.5.2
MCSPI Operational Mode Configuration
- 12.1.5.5.2.1
MCSPI Operational Modes
- 12.1.5.5.2.1.1 Common Transfer Sequence
- 12.1.5.5.2.1.2 End of Transfer Sequences
- 12.1.5.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
- 12.1.5.5.2.1.4 Transmit-Only (Controller and Peripheral)
- 12.1.5.5.2.1.5 Controller Normal Receive-Only
- 12.1.5.5.2.1.6 Controller Turbo Receive-Only
- 12.1.5.5.2.1.7 Peripheral Receive-Only
- 12.1.5.5.2.1.8
Transfer Procedures With FIFO
- 12.1.5.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
- 12.1.5.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
- 12.1.5.5.2.1.8.3 Transmit-and-Receive With Word Count
- 12.1.5.5.2.1.8.4 Transmit-and-Receive Without Word Count
- 12.1.5.5.2.1.8.5 Transmit-Only
- 12.1.5.5.2.1.8.6 Receive-Only With Word Count
- 12.1.5.5.2.1.8.7 Receive-Only Without Word Count
- 12.1.5.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
- 12.1.5.5.2.1
MCSPI Operational Modes
- 12.1.5.6 MCSPI Registers
- 12.1.6
Universal Asynchronous Receiver/Transmitter (UART)
- 12.1.6.1 UART Overview
- 12.1.6.2
UART Environment
- 12.1.6.2.1 UART Functional Interfaces
- 12.1.6.2.2 RS-485 Functional Interfaces
- 12.1.6.2.3 IrDA Functional Interfaces
- 12.1.6.2.4 CIR Functional Interfaces
- 12.1.6.3 UART Integration
- 12.1.6.4
UART Functional Description
- 12.1.6.4.1 UART Block Diagram
- 12.1.6.4.2 UART Clock Configuration
- 12.1.6.4.3 UART Software Reset
- 12.1.6.4.4 UART Power Management
- 12.1.6.4.5 UART Interrupt Requests
- 12.1.6.4.6 UART FIFO Management
- 12.1.6.4.7 UART Mode Selection
- 12.1.6.4.8
UART Protocol Formatting
- 12.1.6.4.8.1
UART Mode
- 12.1.6.4.8.1.1 UART Clock Generation: Baud Rate Generation
- 12.1.6.4.8.1.2 Choosing the Appropriate Divisor Value
- 12.1.6.4.8.1.3 UART Data Formatting
- 12.1.6.4.8.2 RS-485 Mode
- 12.1.6.4.8.3
IrDA Mode
- 12.1.6.4.8.3.1 IrDA Clock Generation: Baud Generator
- 12.1.6.4.8.3.2 Choosing the Appropriate Divisor Value
- 12.1.6.4.8.3.3
IrDA Data Formatting
- 12.1.6.4.8.3.3.1 IR RX Polarity Control
- 12.1.6.4.8.3.3.2 IrDA Reception Control
- 12.1.6.4.8.3.3.3 IR Address Checking
- 12.1.6.4.8.3.3.4 Frame Closing
- 12.1.6.4.8.3.3.5 Store and Controlled Transmission
- 12.1.6.4.8.3.3.6 Error Detection
- 12.1.6.4.8.3.3.7 Underrun During Transmission
- 12.1.6.4.8.3.3.8 Overrun During Receive
- 12.1.6.4.8.3.3.9 Status FIFO
- 12.1.6.4.8.3.3.10 Multi-drop Parity Mode with Address Match
- 12.1.6.4.8.3.3.11 Time-guard
- 12.1.6.4.8.3.4 SIR Mode Data Formatting
- 12.1.6.4.8.3.5 MIR and FIR Mode Data Formatting
- 12.1.6.4.8.4 CIR Mode
- 12.1.6.4.8.1
UART Mode
- 12.1.6.5
UART Programming Guide
- 12.1.6.5.1 UART Global Initialization
- 12.1.6.5.2 UART Mode selection
- 12.1.6.5.3 UART Submode selection
- 12.1.6.5.4 UART Load FIFO trigger and DMA mode settings
- 12.1.6.5.5 UART Protocol, Baud rate and interrupt settings
- 12.1.6.5.6 UART Hardware and Software Flow Control Configuration
- 12.1.6.5.7 IrDA Programming Model
- 12.1.6.6 UART Registers
- 12.1.1
Analog-to-Digital Converter (ADC)
- 12.2
High-speed Serial Interfaces
- 12.2.1
Gigabit Ethernet MAC (MCU_CPSW0)
- 12.2.1.1 MCU_CPSW0 Overview
- 12.2.1.2 MCU_CPSW0 Environment
- 12.2.1.3 MCU_CPSW0 Integration
- 12.2.1.4
MCU_CPSW0 Functional
Description
- 12.2.1.4.1 Functional Block Diagram
- 12.2.1.4.2 CPSW Ports
- 12.2.1.4.3 Clocking
- 12.2.1.4.4 Software IDLE
- 12.2.1.4.5 Interrupt Functionality
- 12.2.1.4.6
CPSW_2G
- 12.2.1.4.6.1
Address Lookup Engine (ALE)
- 12.2.1.4.6.1.1 Error Handling
- 12.2.1.4.6.1.2 Bypass Operations
- 12.2.1.4.6.1.3 OUI Deny or Accept
- 12.2.1.4.6.1.4 Statistics Counting
- 12.2.1.4.6.1.5 Automotive Security Features
- 12.2.1.4.6.1.6 CPSW Switching Solutions
- 12.2.1.4.6.1.7 VLAN Routing and OAM Operations
- 12.2.1.4.6.1.8 Supervisory packets
- 12.2.1.4.6.1.9
Address Table Entry
- 12.2.1.4.6.1.9.1 Free Table Entry
- 12.2.1.4.6.1.9.2 Multicast Address Table Entry
- 12.2.1.4.6.1.9.3 VLAN/Multicast Address Table Entry
- 12.2.1.4.6.1.9.4 Unicast Address Table Entry
- 12.2.1.4.6.1.9.5 OUI Unicast Address Table Entry
- 12.2.1.4.6.1.9.6 VLAN/Unicast Address Table Entry
- 12.2.1.4.6.1.9.7 VLAN Table Entry
- 12.2.1.4.6.1.10 ALE Policing and Classification
- 12.2.1.4.6.1.11 DSCP
- 12.2.1.4.6.1.12 Packet Forwarding Processes
- 12.2.1.4.6.1.13 VLAN Aware Mode
- 12.2.1.4.6.1.14 VLAN Unaware Mode
- 12.2.1.4.6.2 Packet Priority Handling
- 12.2.1.4.6.3 CPPI Port Ingress
- 12.2.1.4.6.4 Packet CRC Handling
- 12.2.1.4.6.5 FIFO Memory Control
- 12.2.1.4.6.6 FIFO Transmit Queue Control
- 12.2.1.4.6.7 Intersperced Express Traffic (IET – P802.3br/D2.0)
- 12.2.1.4.6.8
Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
- 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
- 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
- 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
- 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
- 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
- 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
- 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
- 12.2.1.4.6.9 Audio Video Bridging
- 12.2.1.4.6.10
Ethernet MAC Sliver
- 12.2.1.4.6.10.1
1947
- 12.2.1.4.6.10.1.1
1948
- 2.1.4.6.10.1.1.1 CRC Insertion
- 2.1.4.6.10.1.1.2 MTXER
- 2.1.4.6.10.1.1.3 Adaptive Performance Optimization (APO)
- 2.1.4.6.10.1.1.4 Inter-Packet-Gap Enforcement
- 2.1.4.6.10.1.1.5 Back Off
- 2.1.4.6.10.1.1.6 Programmable Transmit Inter-Packet Gap
- 2.1.4.6.10.1.1.7 Speed, Duplex and Pause Frame Support Negotiation
- 12.2.1.4.6.10.1.1
1948
- 12.2.1.4.6.10.2 RMII Interface
- 12.2.1.4.6.10.3 RGMII Interface
- 12.2.1.4.6.10.4 Frame Classification
- 12.2.1.4.6.10.5 Receive FIFO Architecture
- 12.2.1.4.6.10.1
1947
- 12.2.1.4.6.11 Embedded Memories
- 12.2.1.4.6.12 Memory Error Detection and Correction
- 12.2.1.4.6.13 Ethernet Port Flow Control
- 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
- 12.2.1.4.6.15 Ethernet Switch Latency
- 12.2.1.4.6.16 MAC Emulation Control
- 12.2.1.4.6.17 MAC Command IDLE
- 12.2.1.4.6.18
CPSW Network Statistics
- 12.2.1.4.6.18.1
Rx-only Statistics Descriptions
- 12.2.1.4.6.18.1.1 Good Rx Frames (Offset = 3A000h - Port 0 or Offset = 3A200h - Port 1)
- 12.2.1.4.6.18.1.2 Broadcast Rx Frames (Offset = 3A004h - Port 0 or Offset = 3A204h - Port 1)
- 12.2.1.4.6.18.1.3 Multicast Rx Frames (Offset = 3A008h - Port 0 or Offset = 3A208h - Port 1)
- 12.2.1.4.6.18.1.4 Pause Rx Frames (Offset = 3A20Ch - Port 1)
- 12.2.1.4.6.18.1.5 Rx CRC Errors (Offset = 3A010h - Port 0 or Offset = 3A210h - Port 1)
- 12.2.1.4.6.18.1.6 Rx Align/Code Errors (Offset = 3A214h - Port 1)
- 12.2.1.4.6.18.1.7 Oversize Rx Frames (Offset = 3A018h - Port 0 or Offset = 3A218h - Port 1)
- 12.2.1.4.6.18.1.8 Rx Jabbers (Offset = 3A21Ch - Port 1)
- 12.2.1.4.6.18.1.9 Undersize (Short) Rx Frames (Offset = 3A020h- Port 0 or Offset = 3A220h - Port 1)
- 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h - Port 0 or Offset = 3A224h - Port 1)
- 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A25Ch - Port 1)
- 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h - Port 0 or Offset = 3A228h - Port 1)
- 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch - Port 0 or Offset = 3A22Ch - Port 1)
- 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h - Port 0 or Offset = 3A230h - Port 1)
- 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h - Port 0 or Offset = 3A284h - Port 1)
- 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h - Port 0 or Offset = 3A288h - Port 1)
- 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch - Port 0 or Offset = 3A28Ch - Port 1)
- 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h - Port 0 or Offset = 3A290h - Port 1)
- 12.2.1.4.6.18.1.19
ALE VLAN Ingress Check Drop (Offset = 3A094h - Port 0 or Offset = 3A294h - Port 1)
- 2.1.4.6.18.1.19.1 ALE DA=SA Drop (Offset = 3A098h - Port 0 or Offset = 3A298h - Port 1)
- 2.1.4.6.18.1.19.2 Block Address Drop (Offset = 3A09Ch - Port 0 or Offset = 3A29Ch - Port 1)
- 2.1.4.6.18.1.19.3 ALE Secure Drop (Offset = 3A0A0h - Port 0 or Offset = 3A2A0h - Port 1)
- 2.1.4.6.18.1.19.4 ALE Authentication Drop (Offset = 3A0A4h - Port 0 or Offset = 3A2A4h - Port 1)
- 2.1.4.6.18.1.19.5 ALE Unknown Unicast (Offset = 3A0A8h - Port 0 or Offset = 3A2A8h - Port 1)
- 2.1.4.6.18.1.19.6 ALE Unknown Unicast Bytecount (Offset = 3A0ACh - Port 0 or Offset = 3A2ACh - Port 1)
- 2.1.4.6.18.1.19.7 ALE Unknown Multicast (Offset = 3A0B0h - Port 0 or Offset = 3A2B0h - Port 1)
- 2.1.4.6.18.1.19.8 ALE Unknown Multicast Bytecount (Offset = 3A0B4h - Port 0 or Offset = 3A2B4h - Port 1)
- 2.1.4.6.18.1.19.9 ALE Unknown Broadcast (Offset = 3A0B8h - Port 0 or Offset = 3A2B8h - Port 1)
- 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh - Port 0 or Offset = 3A2BCh - Port 1)
- 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h - Port 0 or Offset = 3A2C0h - Port 1)
- 12.2.1.4.6.18.2 ALE Policer Match Red (Offset = 3A0C4h - Port 0 or Offset = 3A2C4h - Port 1)
- 12.2.1.4.6.18.3 ALE Policer Match Yellow (Offset = 3A0C8h - Port 0 or Offset = 3A2C8h - Port 1)
- 12.2.1.4.6.18.4 IET Receive Assembly Error (Offset = 3A140h - Port 0 or Offset = 3A340h - Port 1)
- 12.2.1.4.6.18.5 IET Receive Assembly OK (Offset = 3A144h - Port 0 or Offset = 3A344h - Port 1)
- 12.2.1.4.6.18.6 IET Receive SMD Error (Offset = 3A148h - Port 0 or Offset = 3A348h - Port 1)
- 12.2.1.4.6.18.7 IET Receive Merge Fragment Count (Offset = 3A14Ch - Port 0 or Offset = 3A34Ch - Port 1)
- 12.2.1.4.6.18.8
Tx-only Statistics Descriptions
- 12.2.1.4.6.18.8.1 Good Tx Frames (Offset = 3A034h - Port 0 or Offset = 3A234h - Port 1)
- 12.2.1.4.6.18.8.2 Broadcast Tx Frames (Offset = 3A038h - Port 0 or Offset = 3A238h - Port 1)
- 12.2.1.4.6.18.8.3 Multicast Tx Frames (Offset = 3A03Ch - Port 0 or Offset = 3A23Ch - Port 1)
- 12.2.1.4.6.18.8.4 Pause Tx Frames (Offset = 3A240h - Port 1)
- 12.2.1.4.6.18.8.5 Deferred Tx Frames (Offset = 3A244h - Port 1)
- 12.2.1.4.6.18.8.6 Collisions (Offset = 3A248h - Port 1)
- 12.2.1.4.6.18.8.7 Single Collision Tx Frames (Offset = 3A24Ch - Port 1)
- 12.2.1.4.6.18.8.8 Multiple Collision Tx Frames (Offset = 3A250h - Port 1)
- 12.2.1.4.6.18.8.9 Excessive Collisions (Offset = 3A254h - Port 1)
- 12.2.1.4.6.18.8.10 Late Collisions (Offset = 3A258h - Port 1)
- 12.2.1.4.6.18.8.11 Carrier Sense Errors (Offset = 3A260h - Port 1)
- 12.2.1.4.6.18.8.12 Tx Octets (Offset = 3A064h - Port 0 or Offset = 3A264h - Port 1 )
- 12.2.1.4.6.18.8.13 Transmit Priority 0-7 (Offset = 3A380h to 3A3A8h - Port 1)
- 12.2.1.4.6.18.8.14 Transmit Priority 0-7 Drop (Offset = 3A3C0h to 3A3E8 - Port 1)
- 12.2.1.4.6.18.8.15 Tx Memory Protect Errors (Offset = 3A17Ch - Port 0 or Offset = 3A37Ch - Port 1)
- 12.2.1.4.6.18.8.16 IET Transmit Merge Hold Count (Offset = 3A350h - Port 1)
- 12.2.1.4.6.18.8.17 IET Transmit Merge Fragment Count (Offset = 3A154h - Port 0 or Offset = 3A354h - Port 1)
- 12.2.1.4.6.18.9
Rx- and Tx (Shared) Statistics Descriptions
- 12.2.1.4.6.18.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h - Port 0 or Offset = 3A268h - Port 1)
- 12.2.1.4.6.18.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch - Port 0 or Offset = 3A26Ch - Port 1)
- 12.2.1.4.6.18.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h - Port 0 or Offset = 3A270h - Port 1)
- 12.2.1.4.6.18.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h - Port 0 or Offset = 3A274h - Port 1)
- 12.2.1.4.6.18.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h - Port 0 or Offset = 3A278h - Port 1)
- 12.2.1.4.6.18.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch - Port 0 or Offset = 3A27Ch - Port 1)
- 12.2.1.4.6.18.9.7 Net Octets (Offset = 3A080h - Port 0 or Offset = 3A280h - Port 1)
- 12.2.1.4.6.18.10 2047
- 12.2.1.4.6.18.1
Rx-only Statistics Descriptions
- 12.2.1.4.6.1
Address Lookup Engine (ALE)
- 12.2.1.4.7
Common Platform Time Sync (CPTS)
- 12.2.1.4.7.1 MCU_CPSW0 CPTS Integration
- 12.2.1.4.7.2 CPTS Architecture
- 12.2.1.4.7.3 CPTS Initialization
- 12.2.1.4.7.4 32-bit Time Stamp Value
- 12.2.1.4.7.5 64-bit Time Stamp Value
- 12.2.1.4.7.6 64-Bit Timestamp Nudge
- 12.2.1.4.7.7 64-bit Timestamp PPM
- 12.2.1.4.7.8 Event FIFO
- 12.2.1.4.7.9 Timestamp Compare Output
- 12.2.1.4.7.10 Timestamp Sync Output
- 12.2.1.4.7.11 Timestamp GENFn Output
- 12.2.1.4.7.12 Timestamp ESTFn
- 12.2.1.4.7.13 Time Sync Events
- 12.2.1.4.7.14 Timestamp Compare Event
- 12.2.1.4.7.15 Host Transmit Event
- 12.2.1.4.7.16 CPTS Interrupt Handling
- 12.2.1.4.8 CPPI Streaming Packet Interface
- 12.2.1.4.9 MII Management Interface (MDIO)
- 12.2.1.5 MCU_CPSW0 Programming Guide
- 12.2.1.6
MCU_CPSW0 Registers
- 12.2.1.6.1 MCU_CPSW0_NUSS Subsystem (SS) Registers
- 12.2.1.6.2 MCU_CPSW0_SGMII Registers
- 12.2.1.6.3 MCU_CPSW0_MDIO Registers
- 12.2.1.6.4 MCU_CPSW0_CPTS Registers
- 12.2.1.6.5 MCU_CPSW0_CONTROL Registers
- 12.2.1.6.6 MCU_CPSW0_CPINT Registers
- 12.2.1.6.7 MCU_CPSW0_RAM Registers
- 12.2.1.6.8 MCU_CPSW0_STAT0 Registers
- 12.2.1.6.9 MCU_CPSW0_STAT1 Registers
- 12.2.1.6.10 MCU_CPSW0_ALE Registers
- 12.2.1.6.11 MCU_CPSW0_ECC Registers
- 12.2.2
Gigabit Ethernet Switch (CPSW0)
- 12.2.2.1 CPSW0 Overview
- 12.2.2.2 CPSW0 Environment
- 12.2.2.3 CPSW0 Integration
- 12.2.2.4
CPSW0 Functional Description
- 12.2.2.4.1 Functional Block Diagram
- 12.2.2.4.2 CPSW Ports
- 12.2.2.4.3 Clocking
- 12.2.2.4.4 Software IDLE
- 12.2.2.4.5 Interrupt Functionality
- 12.2.2.4.6
CPSW_5X
- 12.2.2.4.6.1
Address Lookup Engine (ALE)
- 12.2.2.4.6.1.1 Error Handling
- 12.2.2.4.6.1.2 Bypass Operations
- 12.2.2.4.6.1.3 OUI Deny or Accept
- 12.2.2.4.6.1.4 Statistics Counting
- 12.2.2.4.6.1.5 Automotive Security Features
- 12.2.2.4.6.1.6 CPSW Switching Solutions
- 12.2.2.4.6.1.7 VLAN Routing and OAM Operations
- 12.2.2.4.6.1.8 Supervisory packets
- 12.2.2.4.6.1.9
Address Table Entry
- 12.2.2.4.6.1.9.1 Free Table Entry
- 12.2.2.4.6.1.9.2 Multicast Address Table Entry (Bit 40 == 0)
- 12.2.2.4.6.1.9.3 Multicast Address Table Entry (Bit 40 == 1)
- 12.2.2.4.6.1.9.4 VLAN Unicast Address Table Entry (Bit 40 == 0)
- 12.2.2.4.6.1.9.5 OUI Unicast Address Table Entry
- 12.2.2.4.6.1.9.6 VLAN/Unicast Address Table Entry (Bit 40 == 0)
- 12.2.2.4.6.1.9.7 VLAN/ Multicast Address Table Entry (Bit 40 == 1)
- 12.2.2.4.6.1.9.8 Inner VLAN Table Entry
- 12.2.2.4.6.1.9.9 Outer VLAN Table Entry
- 12.2.2.4.6.1.9.10 EtherType Table Entry
- 12.2.2.4.6.1.9.11 IPv4 Table Entry
- 12.2.2.4.6.1.9.12 IPv6 Table Entry High
- 12.2.2.4.6.1.9.13 IPv6 Table Entry Low
- 12.2.2.4.6.1.10 Multicast Address
- 12.2.2.4.6.1.11 Supervisory Packets
- 12.2.2.4.6.1.12 Aging and Auto Aging
- 12.2.2.4.6.1.13 ALE Policing and Classification
- 12.2.2.4.6.1.14 Mirroring
- 12.2.2.4.6.1.15 Trunking
- 12.2.2.4.6.1.16 DSCP
- 12.2.2.4.6.1.17 Packet Forwarding Processes
- 12.2.2.4.6.1.18 VLAN Aware Mode
- 12.2.2.4.6.1.19 VLAN Unaware Mode
- 12.2.2.4.6.2 Packet Priority Handling
- 12.2.2.4.6.3 CPPI Port Ingress
- 12.2.2.4.6.4 Packet CRC Handling
- 12.2.2.4.6.5 FIFO Memory Control
- 12.2.2.4.6.6 FIFO Transmit Queue Control
- 12.2.2.4.6.7 Intersperced Express Traffic (IET – P802.3br/D2.0)
- 12.2.2.4.6.8
Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
- 12.2.2.4.6.8.1 Enhanced Scheduled Traffic Overview
- 12.2.2.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
- 12.2.2.4.6.8.3 Enhanced Scheduled Traffic Time Interval
- 12.2.2.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
- 12.2.2.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
- 12.2.2.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
- 12.2.2.4.6.9 Audio Video Bridging
- 12.2.2.4.6.10
Ethernet MAC Sliver
- 12.2.2.4.6.10.1 CRC Insertion
- 12.2.2.4.6.10.2 MTXER
- 12.2.2.4.6.10.3 Adaptive Performance Optimization (APO)
- 12.2.2.4.6.10.4 Inter-Packet-Gap Enforcement
- 12.2.2.4.6.10.5 Back Off
- 12.2.2.4.6.10.6 Programmable Transmit Inter-Packet Gap
- 12.2.2.4.6.10.7 Speed, Duplex and Pause Frame Support Negotiation
- 12.2.2.4.6.10.8 RMII Interface
- 12.2.2.4.6.10.9 RGMII Interface
- 12.2.2.4.6.10.10 Frame Classification
- 12.2.2.4.6.10.11 Receive FIFO Architecture
- 12.2.2.4.6.11 Embedded Memories
- 12.2.2.4.6.12 Memory Error Detection and Correction
- 12.2.2.4.6.13 Ethernet Port Flow Control
- 12.2.2.4.6.14 PFC Trigger Rules
- 12.2.2.4.6.15 Energy Efficient Ethernet Support (802.3az)
- 12.2.2.4.6.16 Ethernet Switch Latency
- 12.2.2.4.6.17 MAC Emulation Control
- 12.2.2.4.6.18 MAC Command IDLE
- 12.2.2.4.6.19
CPSW Network Statistics
- 12.2.2.4.6.19.1
Rx-only Statistics Descriptions
- 12.2.2.4.6.19.1.1 Good Rx Frames (Offset = 3A000h)
- 12.2.2.4.6.19.1.2 Broadcast Rx Frames (Offset = 3A004h)
- 12.2.2.4.6.19.1.3 Multicast Rx Frames (Offset = 3A008h)
- 12.2.2.4.6.19.1.4 Pause Rx Frames (Offset = 3A00Ch)
- 12.2.2.4.6.19.1.5 Rx CRC Errors (Offset = 3A010h)
- 12.2.2.4.6.19.1.6 Rx Align/Code Errors (Offset = 3A014h)
- 12.2.2.4.6.19.1.7 Oversize Rx Frames (Offset = 3A018h)
- 12.2.2.4.6.19.1.8 Rx Jabbers (Offset = 3A01Ch)
- 12.2.2.4.6.19.1.9 Undersize (Short) Rx Frames (Offset = 3A020h)
- 12.2.2.4.6.19.1.10 Rx Fragments (Offset = 3A024h)
- 12.2.2.4.6.19.1.11 RX IPG Error
- 12.2.2.4.6.19.1.12 ALE Drop (Offset = 3A028h)
- 12.2.2.4.6.19.1.13 ALE Overrun Drop (Offset = 3A02Ch)
- 12.2.2.4.6.19.1.14 Rx Octets (Offset = 3A030h)
- 12.2.2.4.6.19.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
- 12.2.2.4.6.19.1.16 Portmask Drop (Offset = 3A088h)
- 12.2.2.4.6.19.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
- 12.2.2.4.6.19.1.18 ALE Rate Limit Drop (Offset = 3A090h)
- 12.2.2.4.6.19.1.19
ALE VLAN Ingress Check Drop (Offset = 3A094h)
- 2.2.4.6.19.1.19.1 ALE DA=SA Drop (Offset = 3A098h)
- 2.2.4.6.19.1.19.2 Block Address Drop (Offset = 3A09Ch)
- 2.2.4.6.19.1.19.3 ALE Secure Drop (Offset = 3A0A0h)
- 2.2.4.6.19.1.19.4 ALE Authentication Drop (Offset = 3A0A4h)
- 2.2.4.6.19.1.19.5 ALE Unknown Unicast (Offset = 3A0A8h)
- 2.2.4.6.19.1.19.6 ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
- 2.2.4.6.19.1.19.7 ALE Unknown Multicast (Offset = 3A0B0h)
- 2.2.4.6.19.1.19.8 ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
- 2.2.4.6.19.1.19.9 ALE Unknown Broadcast (Offset = 3A0B8h)
- 2.2.4.6.19.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
- 2.2.4.6.19.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
- 12.2.2.4.6.19.2 ALE Policer Match Red (Offset = 3A0C4h)
- 12.2.2.4.6.19.3 ALE Policer Match Yellow (Offset = 3A0C8h)
- 12.2.2.4.6.19.4 IET Receive Assembly Error (Offset = 3A140h)
- 12.2.2.4.6.19.5 IET Receive Assembly OK (Offset = 3A144h)
- 12.2.2.4.6.19.6 IET Receive SMD Error (Offset = 3A148h)
- 12.2.2.4.6.19.7 IET Receive Merge Fragment Count (Offset = 3A14Ch)
- 12.2.2.4.6.19.8
Tx-only Statistics Descriptions
- 12.2.2.4.6.19.8.1 Good Tx Frames (Offset = 3A034h)
- 12.2.2.4.6.19.8.2 Broadcast Tx Frames (Offset = 3A038h)
- 12.2.2.4.6.19.8.3 Multicast Tx Frames (Offset = 3A03Ch)
- 12.2.2.4.6.19.8.4 Pause Tx Frames (Offset = 3A040h)
- 12.2.2.4.6.19.8.5 Deferred Tx Frames (Offset = 3A044h)
- 12.2.2.4.6.19.8.6 Collisions (Offset = 3A048h)
- 12.2.2.4.6.19.8.7 Single Collision Tx Frames (Offset = 3A04Ch)
- 12.2.2.4.6.19.8.8 Multiple Collision Tx Frames (Offset = 3A050h)
- 12.2.2.4.6.19.8.9 Excessive Collisions (Offset = 3A054h)
- 12.2.2.4.6.19.8.10 Late Collisions (Offset = 3A058h)
- 12.2.2.4.6.19.8.11 Carrier Sense Errors (Offset = 3A060h)
- 12.2.2.4.6.19.8.12 Tx Octets (Offset = 3A064h)
- 12.2.2.4.6.19.8.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
- 12.2.2.4.6.19.8.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8h)
- 12.2.2.4.6.19.8.15 Tx Memory Protect Errors (Offset = 3A17Ch)
- 12.2.2.4.6.19.8.16 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
- 12.2.2.4.6.19.8.17 IET Transmit Merge Hold Count (Offset = 3A150h)
- 12.2.2.4.6.19.9
Rx- and Tx (Shared) Statistics Descriptions
- 12.2.2.4.6.19.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
- 12.2.2.4.6.19.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
- 12.2.2.4.6.19.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
- 12.2.2.4.6.19.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
- 12.2.2.4.6.19.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
- 12.2.2.4.6.19.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
- 12.2.2.4.6.19.9.7 Net Octets (Offset = 3A080h)
- 12.2.2.4.6.19.10 2326
- 12.2.2.4.6.19.1
Rx-only Statistics Descriptions
- 12.2.2.4.6.1
Address Lookup Engine (ALE)
- 12.2.2.4.7
Common Platform Time Sync (CPTS)
- 12.2.2.4.7.1 CPSW0 CPTS Integration
- 12.2.2.4.7.2 CPTS Architecture
- 12.2.2.4.7.3 CPTS Initialization
- 12.2.2.4.7.4 32-bit Time Stamp Value
- 12.2.2.4.7.5 64-bit Time Stamp Value
- 12.2.2.4.7.6 64-Bit Timestamp Nudge
- 12.2.2.4.7.7 64-bit Timestamp PPM
- 12.2.2.4.7.8 Event FIFO
- 12.2.2.4.7.9 Timestamp Compare Output
- 12.2.2.4.7.10 Timestamp Sync Output
- 12.2.2.4.7.11 Timestamp GENFn Output
- 12.2.2.4.7.12 Timestamp ESTFn
- 12.2.2.4.7.13 Time Sync Events
- 12.2.2.4.7.14 Timestamp Compare Event
- 12.2.2.4.7.15 Host Transmit Event
- 12.2.2.4.7.16 CPTS Interrupt Handling
- 12.2.2.4.8 CPPI Streaming Packet Interface
- 12.2.2.4.9 MII Management Interface (MDIO)
- 12.2.2.5 CPSW0 Programming Guide
- 12.2.2.6
CPSW0 Registers
- 12.2.2.6.1 CPSW0_NUSS Subsystem (SS) Registers
- 12.2.2.6.2 CPSW0_SGMII Registers
- 12.2.2.6.3 CPSW0_MDIO Registers
- 12.2.2.6.4 CPSW0_CPTS Registers
- 12.2.2.6.5 CPSW0_CONTROL Registers
- 12.2.2.6.6 CPSW0_CPINT Registers
- 12.2.2.6.7 CPSW0_RAM Registers
- 12.2.2.6.8 CPSW0_STAT Registers
- 12.2.2.6.9 CPSW0_ALE Registers
- 12.2.2.6.10 CPSW0_PCSR Registers
- 12.2.2.6.11 CPSW0_ECC Registers
- 12.2.3
Peripheral Component Interconnect Express (PCIe) Subsystem
- 12.2.3.1 PCIe Subsystem Overview
- 12.2.3.2 PCIe Subsystem Environment
- 12.2.3.3 PCIe Subsystem Integration
- 12.2.3.4
PCIe Subsystem Functional Description
- 12.2.3.4.1 PCIe Subsystem Block Diagram
- 12.2.3.4.2 PCIe Subsystem Reset Schemes
- 12.2.3.4.3 PCIe Subsystem Power Management
- 12.2.3.4.4
PCIe Subsystem Interrupts
- 12.2.3.4.4.1 Interrupts Aggregation
- 12.2.3.4.4.2 Interrupt Generation in EP Mode
- 12.2.3.4.4.3 Interrupt Reception in EP Mode
- 12.2.3.4.4.4 Interrupt Generation in RP Mode
- 12.2.3.4.4.5 Interrupt Reception in RP Mode
- 12.2.3.4.4.6 Common Interrupt Reception in RP and EP Modes
- 12.2.3.4.4.7 ECC Aggregator Interrupts
- 12.2.3.4.4.8 CPTS Interrupt
- 12.2.3.4.5 PCIe Subsystem DMA Support
- 12.2.3.4.6 PCIe Subsystem Transactions
- 12.2.3.4.7 PCIe Subsystem Address Translation
- 12.2.3.4.8 PCIe Subsystem Virtualization Support
- 12.2.3.4.9 PCIe Subsystem Quality-of-Service (QoS)
- 12.2.3.4.10 PCIe Subsystem Precision Time Measurement (PTM)
- 12.2.3.4.11 PCIe Subsystem Loopback
- 12.2.3.4.12 PCIe Subsystem Error Handling
- 12.2.3.4.13 PCIe Subsystem Internal Diagnostics Features
- 12.2.3.4.14 LTSSM State Encoding
- 12.2.3.5
PCIe Subsystem Registers
- 12.2.3.5.1 PCIE_CORE_EP_PF Registers
- 12.2.3.5.2 PCIE_CORE_EP_VF Registers
- 12.2.3.5.3 PCIE_CORE_RP Registers
- 12.2.3.5.4 PCIE_CORE_LM Registers
- 12.2.3.5.5 PCIE_CORE_AXI Registers
- 12.2.3.5.6 PCIE_INTD Registers
- 12.2.3.5.7 PCIE_VMAP Registers
- 12.2.3.5.8 PCIE_CPTS Registers
- 12.2.3.5.9 PCIE_USER_CFG Registers
- 12.2.3.5.10 PCIE_ECC_AGGR0 Registers
- 12.2.3.5.11 PCIE_ECC_AGGR1 Registers
- 12.2.3.5.12 PCIE_DAT0 Registers
- 12.2.3.5.13 PCIE_DAT1 Registers
- 12.2.4 Universal Serial Bus (USB) Subsystem
- 12.2.5 Serializer/Deserializer (SerDes)
- 12.2.1
Gigabit Ethernet MAC (MCU_CPSW0)
- 12.3
Memory Interfaces
- 12.3.1 Flash Subsystem (FSS)
- 12.3.2
Octal Serial Peripheral Interface (OSPI)
- 12.3.2.1 OSPI Overview
- 12.3.2.2 OSPI Environment
- 12.3.2.3 OSPI Integration
- 12.3.2.4
OSPI Functional Description
- 12.3.2.4.1 OSPI Block Diagram
- 12.3.2.4.2 OSPI Modes
- 12.3.2.4.3 OSPI Power Management
- 12.3.2.4.4 Auto HW Polling
- 12.3.2.4.5 Flash Reset
- 12.3.2.4.6 OSPI Memory Regions
- 12.3.2.4.7 OSPI Interrupt Requests
- 12.3.2.4.8 OSPI Data Interface
- 12.3.2.4.9 OSPI Direct Access Controller (DAC)
- 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
- 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
- 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
- 12.3.2.4.13 OSPI Command Translation
- 12.3.2.4.14 Selecting the Flash Instruction Type
- 12.3.2.4.15 OSPI Data Integrity
- 12.3.2.4.16 OSPI PHY Module
- 12.3.2.5
OSPI Programming Guide
- 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
- 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
- 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
- 12.3.2.5.4 Using SPI Legacy Mode
- 12.3.2.5.5 Entering XIP Mode from POR
- 12.3.2.5.6 Entering XIP Mode Otherwise
- 12.3.2.5.7 Exiting XIP Mode
- 12.3.2.6 OSPI Registers
- 12.3.3 HyperBus Interface
- 12.3.4
General-Purpose Memory Controller (GPMC)
- 12.3.4.1 GPMC Overview
- 12.3.4.2 GPMC Environment
- 12.3.4.3 GPMC Integration
- 12.3.4.4
GPMC Functional Description
- 12.3.4.4.1 GPMC Block Diagram
- 12.3.4.4.2 GPMC Clock Configuration
- 12.3.4.4.3 GPMC Power Management
- 12.3.4.4.4 GPMC Interrupt Requests
- 12.3.4.4.5 GPMC Interconnect Port Interface
- 12.3.4.4.6 GPMC Address and Data Bus
- 12.3.4.4.7
GPMC Address Decoder and Chip-Select Configuration
- 12.3.4.4.7.1 Chip-Select Base Address and Region Size
- 12.3.4.4.7.2 Access Protocol
- 12.3.4.4.7.3
External Signals
- 12.3.4.4.7.3.1
WAIT Pin Monitoring Control
- 12.3.4.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
- 12.3.4.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
- 12.3.4.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
- 12.3.4.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
- 12.3.4.4.7.3.1.5 Wait With NAND Device
- 12.3.4.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
- 12.3.4.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
- 12.3.4.4.7.3.2 DIR Pin
- 12.3.4.4.7.3.3 Reset
- 12.3.4.4.7.3.4 Write Protect Signal (nWP)
- 12.3.4.4.7.3.5 Byte Enable (nBE1/nBE0)
- 12.3.4.4.7.3.1
WAIT Pin Monitoring Control
- 12.3.4.4.7.4 Error Handling
- 12.3.4.4.8
GPMC Timing Setting
- 12.3.4.4.8.1 Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
- 12.3.4.4.8.2 nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
- 12.3.4.4.8.3 nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
- 12.3.4.4.8.4 nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
- 12.3.4.4.8.5 nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
- 12.3.4.4.8.6 GPMC_CLKOUT
- 12.3.4.4.8.7 GPMC Output Clock and Control Signals Setup and Hold
- 12.3.4.4.8.8 Access Time (RDACCESSTIME / WRACCESSTIME)
- 12.3.4.4.8.9 Page Burst Access Time (PAGEBURSTACCESSTIME)
- 12.3.4.4.8.10 Bus Keeping Support
- 12.3.4.4.9
GPMC NOR Access Description
- 12.3.4.4.9.1 Asynchronous Access Description
- 12.3.4.4.9.2 Synchronous Access Description
- 12.3.4.4.9.3
Asynchronous and Synchronous Accesses in non-multiplexed Mode
- 12.3.4.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
- 12.3.4.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
- 12.3.4.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
- 12.3.4.4.9.3.4 Synchronous Operations on a non-multiplexed Device
- 12.3.4.4.9.4 Page and Burst Support
- 12.3.4.4.9.5 System Burst vs External Device Burst Support
- 12.3.4.4.10 GPMC pSRAM Access Specificities
- 12.3.4.4.11
GPMC NAND Access Description
- 12.3.4.4.11.1
NAND Memory Device in Byte or 16-bit Word Stream Mode
- 12.3.4.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
- 12.3.4.4.11.1.2 NAND Device Command and Address Phase Control
- 12.3.4.4.11.1.3 Command Latch Cycle
- 12.3.4.4.11.1.4 Address Latch Cycle
- 12.3.4.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
- 12.3.4.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
- 12.3.4.4.11.1.7 Read and Write Access Size Adaptation
- 12.3.4.4.11.2 NAND Device-Ready Pin
- 12.3.4.4.11.3
ECC Calculator
- 12.3.4.4.11.3.1 Hamming Code
- 12.3.4.4.11.3.2
BCH Code
- 12.3.4.4.11.3.2.1 Requirements
- 12.3.4.4.11.3.2.2
Memory Mapping of BCH Codeword
- 3.4.4.11.3.2.2.1 Memory Mapping of Data Message
- 3.4.4.11.3.2.2.2 Memory-Mapping of the ECC
- 3.4.4.11.3.2.2.3
Wrapping Modes
- 4.4.11.3.2.2.3.1 Manual Mode (0x0)
- 4.4.11.3.2.2.3.2 Mode 0x1
- 4.4.11.3.2.2.3.3 Mode 0xA (10)
- 4.4.11.3.2.2.3.4 Mode 0x2
- 4.4.11.3.2.2.3.5 Mode 0x3
- 4.4.11.3.2.2.3.6 Mode 0x7
- 4.4.11.3.2.2.3.7 Mode 0x8
- 4.4.11.3.2.2.3.8 Mode 0x4
- 4.4.11.3.2.2.3.9 Mode 0x9
- 4.4.11.3.2.2.3.10 Mode 0x5
- 4.4.11.3.2.2.3.11 Mode 0xB (11)
- 4.4.11.3.2.2.3.12 Mode 0x6
- 12.3.4.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
- 12.3.4.4.11.4
Prefetch and Write-Posting Engine
- 12.3.4.4.11.4.1 General Facts About the Engine Configuration
- 12.3.4.4.11.4.2 Prefetch Mode
- 12.3.4.4.11.4.3 FIFO Control in Prefetch Mode
- 12.3.4.4.11.4.4 Write-Posting Mode
- 12.3.4.4.11.4.5 FIFO Control in Write-Posting Mode
- 12.3.4.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
- 12.3.4.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
- 12.3.4.4.11.1
NAND Memory Device in Byte or 16-bit Word Stream Mode
- 12.3.4.4.12 GPMC Use Cases and Tips
- 12.3.4.5 GPMC Basic Programming Model
- 12.3.4.6 GPMC Registers
- 12.3.5 Error Location Module (ELM)
- 12.3.6
Multi-Media Card Secure Digital (MMCSD) Interface
- 12.3.6.1 MMCSD Overview
- 12.3.6.2 MMCSD Environment
- 12.3.6.3 MMCSD Integration
- 12.3.6.4
MMCSD Functional Description
- 12.3.6.4.1 Block Diagram
- 12.3.6.4.2 Memory Regions
- 12.3.6.4.3 Interrupt Requests
- 12.3.6.4.4 ECC Support
- 12.3.6.4.5 Advanced DMA
- 12.3.6.4.6
eMMC PHY BIST
- 12.3.6.4.6.1 BIST Overview
- 12.3.6.4.6.2
BIST Modes
- 12.3.6.4.6.2.1 DS Mode
- 12.3.6.4.6.2.2 HS Mode with TXDLY using DLL
- 12.3.6.4.6.2.3 HS Mode with TXDLY using Delay Chain
- 12.3.6.4.6.2.4 DDR50 Mode with TXDLY using DLL
- 12.3.6.4.6.2.5 DDR50 Mode with TXDLY using Delay Chain
- 12.3.6.4.6.2.6 HS200 Mode with TX/RXDLY using DLL
- 12.3.6.4.6.2.7 HS200 Mode with TX/RXDLY using Delay Chain
- 12.3.6.4.6.2.8 HS400 Mode
- 12.3.6.4.6.3 BIST Functionality
- 12.3.6.4.6.4 Signal Interface
- 12.3.6.4.6.5 Programming Flow
- 12.3.6.4.6.6 HS200 BIST Result Check Procedure
- 12.3.6.5
MMCSD Programming Guide
- 12.3.6.5.1
Sequences
- 12.3.6.5.1.1 SD Card Detection
- 12.3.6.5.1.2 SD Clock Control
- 12.3.6.5.1.3 SD Bus Power Control
- 12.3.6.5.1.4 Changing Bus Width
- 12.3.6.5.1.5 Timeout Setting on DAT Line
- 12.3.6.5.1.6 Card Initialization and Identification (for SD I/F)
- 12.3.6.5.1.7 SD Transaction Generation
- 12.3.6.5.1.8 Abort Transaction
- 12.3.6.5.1.9 Changing Bus Speed Mode
- 12.3.6.5.1.10 Error Recovery
- 12.3.6.5.1.11 Wakeup Control (Optional)
- 12.3.6.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
- 12.3.6.5.2 Driver Flow Sequence
- 12.3.6.5.1
Sequences
- 12.3.6.6
MMCSD Registers
- 12.3.6.6.1 MMCSD0 Subsystem Registers
- 12.3.6.6.2 MMCSD0 RX RAM ECC Aggregator Registers
- 12.3.6.6.3 MMCSD0 TX RAM ECC Aggregator Registers
- 12.3.6.6.4 MMCSD0 Host Controller Registers
- 12.3.6.6.5 MMCSD1 Subsystem Registers
- 12.3.6.6.6 MMCSD1 RX RAM ECC Aggregator Registers
- 12.3.6.6.7 MMCSD1 TX RAM ECC Aggregator Registers
- 12.3.6.6.8 MMCSD1 Host Controller Registers
- 12.4
Industrial and Control Interfaces
- 12.4.1
Enhanced Capture (ECAP) Module
- 12.4.1.1 ECAP Overview
- 12.4.1.2 ECAP Environment
- 12.4.1.3 ECAP Integration
- 12.4.1.4
ECAP Functional Description
- 12.4.1.4.1
Capture and APWM Operating Modes
- 12.4.1.4.1.1
ECAP Capture Mode Description
- 12.4.1.4.1.1.1 ECAP Event Prescaler
- 12.4.1.4.1.1.2 ECAP Edge Polarity Select and Qualifier
- 12.4.1.4.1.1.3 ECAP Continuous/One-Shot Control
- 12.4.1.4.1.1.4 ECAP 32-Bit Counter and Phase Control
- 12.4.1.4.1.1.5 CAP1-CAP4 Registers
- 12.4.1.4.1.1.6 ECAP Interrupt Control
- 12.4.1.4.1.1.7 ECAP Shadow Load and Lockout Control
- 12.4.1.4.1.2 ECAP APWM Mode Operation
- 12.4.1.4.1.1
ECAP Capture Mode Description
- 12.4.1.4.2 Summary of ECAP Functional Registers
- 12.4.1.4.1
Capture and APWM Operating Modes
- 12.4.1.5
ECAP Use Cases
- 12.4.1.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
- 12.4.1.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
- 12.4.1.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
- 12.4.1.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
- 12.4.1.5.5 Application of the APWM Mode
- 12.4.1.6 ECAP Registers
- 12.4.2
Enhanced Pulse Width Modulation (EPWM) Module
- 12.4.2.1 EPWM Overview
- 12.4.2.2 EPWM Environment
- 12.4.2.3 EPWM Integration
- 12.4.2.4
EPWM Functional Description
- 12.4.2.4.1 EPWM Submodule Features
- 12.4.2.4.2 EPWM Time-Base (TB) Submodule
- 12.4.2.4.3 EPWM Counter-Compare (CC) Submodule
- 12.4.2.4.4 EPWM Action-Qualifier (AQ) Submodule
- 12.4.2.4.5 EPWM Dead-Band Generator (DB) Submodule
- 12.4.2.4.6 EPWM-Chopper (PC) Submodule
- 12.4.2.4.7 EPWM Trip-Zone (TZ) Submodule
- 12.4.2.4.8 EPWM Event-Trigger (ET) Submodule
- 12.4.2.4.9 EPWM High Resolution (HRPWM) Submodule
- 12.4.2.4.10 EPWM / HRPWM Functional Register Groups
- 12.4.2.4.11 Proper EPWM Interrupt Initialization Procedure
- 12.4.2.5 EPWM Registers
- 12.4.3
Enhanced Quadrature Encoder Pulse (EQEP) Module
- 12.4.3.1 EQEP Overview
- 12.4.3.2 EQEP Environment
- 12.4.3.3 EQEP Integration
- 12.4.3.4
EQEP Functional Description
- 12.4.3.4.1 EQEP Inputs
- 12.4.3.4.2 EQEP Quadrature Decoder Unit (QDU)
- 12.4.3.4.3
EQEP Position Counter and Control Unit (PCCU)
- 12.4.3.4.3.1
EQEP Position Counter Operating Modes
- 12.4.3.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
- 12.4.3.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
- 12.4.3.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
- 12.4.3.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
- 12.4.3.4.3.2 EQEP Position Counter Latch
- 12.4.3.4.3.3 EQEP Position Counter Initialization
- 12.4.3.4.3.4 EQEP Position-Compare Unit
- 12.4.3.4.3.1
EQEP Position Counter Operating Modes
- 12.4.3.4.4 EQEP Edge Capture Unit
- 12.4.3.4.5 EQEP Watchdog
- 12.4.3.4.6 Unit Timer Base
- 12.4.3.4.7 EQEP Interrupt Structure
- 12.4.3.4.8 Summary of EQEP Functional Registers
- 12.4.3.5 EQEP Registers
- 12.4.4
Controller Area Network (MCAN)
- 12.4.4.1 MCAN Overview
- 12.4.4.2 MCAN Environment
- 12.4.4.3 MCAN Integration
- 12.4.4.4
MCAN Functional Description
- 12.4.4.4.1 Module Clocking Requirements
- 12.4.4.4.2 Interrupt and DMA Requests
- 12.4.4.4.3
Operating Modes
- 12.4.4.4.3.1 Software Initialization
- 12.4.4.4.3.2 Normal Operation
- 12.4.4.4.3.3 CAN FD Operation
- 12.4.4.4.3.4 Transmitter Delay Compensation
- 12.4.4.4.3.5 Restricted Operation Mode
- 12.4.4.4.3.6 Bus Monitoring Mode
- 12.4.4.4.3.7 Disabled Automatic Retransmission (DAR) Mode
- 12.4.4.4.3.8 Power Down (Sleep Mode)
- 12.4.4.4.3.9 Test Modes
- 12.4.4.4.4 Timestamp Generation
- 12.4.4.4.5 Timeout Counter
- 12.4.4.4.6 ECC Support
- 12.4.4.4.7 Rx Handling
- 12.4.4.4.8 Tx Handling
- 12.4.4.4.9 FIFO Acknowledge Handling
- 12.4.4.4.10 Message RAM
- 12.4.4.5 MCAN Registers
- 12.4.1
Enhanced Capture (ECAP) Module
- 12.5 Audio Interfaces
- 12.6
Timer Modules
- 12.6.1 Global Timebase Counter (GTC)
- 12.6.2 Windowed Watchdog Timer (WWDT)
- 12.6.3
Timers
- 12.6.3.1 Timers Overview
- 12.6.3.2 Timers Environment
- 12.6.3.3 Timers Integration
- 12.6.3.4
Timers Functional Description
- 12.6.3.4.1 Timer Block Diagram
- 12.6.3.4.2 Timer Power Management
- 12.6.3.4.3 Timer Software Reset
- 12.6.3.4.4 Timer Interrupts
- 12.6.3.4.5 Timer Mode Functionality
- 12.6.3.4.6 Timer Capture Mode Functionality
- 12.6.3.4.7 Timer Compare Mode Functionality
- 12.6.3.4.8 Timer Prescaler Functionality
- 12.6.3.4.9 Timer Pulse-Width Modulation
- 12.6.3.4.10 Timer Counting Rate
- 12.6.3.4.11 Timer Under Emulation
- 12.6.3.4.12 Accessing Timer Registers
- 12.6.3.4.13 Timer Posted Mode Selection
- 12.6.3.5 Timers Low-Level Programming Models
- 12.6.3.6 Timers Registers
- 12.7
Internal Diagnostics Modules
- 12.7.1
Dual Clock Comparator (DCC)
- 12.7.1.1 DCC Overview
- 12.7.1.2 DCC Integration
- 12.7.1.3
DCC Functional Description
- 12.7.1.3.1 DCC Counter Operation
- 12.7.1.3.2 DCC Low Power Mode Operation
- 12.7.1.3.3 DCC Suspend Mode Behavior
- 12.7.1.3.4 DCC Single-Shot Mode
- 12.7.1.3.5 DCC Continuous mode
- 12.7.1.3.6 DCC Control and count hand-off across clock domains
- 12.7.1.3.7 DCC Error Trajectory record
- 12.7.1.3.8 DCC Count read registers
- 12.7.1.4 DCC Registers
- 12.7.2
Error Signaling Module (ESM)
- 12.7.2.1 ESM Overview
- 12.7.2.2 ESM Environment
- 12.7.2.3 ESM Integration
- 12.7.2.4
ESM Functional Description
- 12.7.2.4.1 ESM Interrupt Requests
- 12.7.2.4.2 ESM Error Event Inputs
- 12.7.2.4.3 ESM Error Pin Output
- 12.7.2.4.4 ESM Minimum Time Interval
- 12.7.2.4.5 ESM Protection for Registers
- 12.7.2.4.6 ESM Clock Stop
- 12.7.2.5 ESM Registers
- 12.7.3
Memory Cyclic Redundancy Check (MCRC) Controller
- 12.7.3.1 MCRC Overview
- 12.7.3.2 MCRC Integration
- 12.7.3.3
MCRC Functional Description
- 12.7.3.3.1 MCRC Block Diagram
- 12.7.3.3.2 MCRC General Operation
- 12.7.3.3.3 MCRC Modes of Operation
- 12.7.3.3.4 PSA Signature Register
- 12.7.3.3.5 PSA Sector Signature Register
- 12.7.3.3.6 CRC Value Register
- 12.7.3.3.7 Raw Data Register
- 12.7.3.3.8 Example DMA Controller Setup
- 12.7.3.3.9 Pattern Count Register
- 12.7.3.3.10 Sector Count Register/Current Sector Register
- 12.7.3.3.11 Interrupts
- 12.7.3.3.12 Power Down Mode
- 12.7.3.3.13 Emulation
- 12.7.3.4 MCRC Programming Examples
- 12.7.3.5 MCRC Registers
- 12.7.4 ECC Aggregator
- 12.7.1
Dual Clock Comparator (DCC)
- 12.1
General Connectivity Peripherals
- 13On-Chip Debug
- 14Revision History
- IMPORTANT NOTICE
Technical Reference Manual
J7200 DRA821 Processor
Texas Instruments Families of
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About This Manual
This Technical Reference Manual (TRM) details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device.
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1 Introduction
This chapter introduces the features, subsystems, and architecture of the J7200 DRA821 high-performance System-on-Chip (SoC).
Note:
This document describes the Superset architecture, processors and peripherals of the J7200 Family of SoCs, which are part of the K3 Multicore SoC architecture platform. Not all features are available on each family of devices. The superset J7200 devices are available for preproduction software development. Software should constrain the features used to match the intended production device. For more information on the specific features, processors and peripherals available on a particular device, refer to the Device Comparison table in the corresponding device-specific Data sheet.
The J7200 Processor Platforms are hereinafter commonly referred to as J7200 platform, device, or SoC.
TI limits support for this family of SoCs to features that are supported via Software Development Kits (SDK). The SDK “build sheet” is available for download as part of each SDK and should be referenced to understand the subset of SoC hardware functionality that is available in software:
1.1 Device Overview
The DRA821 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products.
It is designed as a low power, high performance and highly integrated device architecture, adding significant enhancement on processing power, with integrated diagnostics, functional safety and state of the art security features and coherent memory support.
Some of the main distinguished characteristics of the device are:
- 64-bit architecture with virtualization and coherent memory support, which leverages full processing capability of 64-bit Arm®Cortex®-A72
- Integration of a general-purpose microcontroller unit (MCU) with a dual Arm® Cortex®-R5F MCU subsystem, available for general purpose use as two cores or in lockstep, intended to help customers achieve functional safety goals for their end products
- Integration of hardware features that help applications to achieve functional safety mechanisms
- Robust security architecture with sandboxed DMSC controller managing all secure configurations with high performance client-server messaging scheme between secure DMSC and all cores
- Simplified solution for power supply management, enabling lower cost system solution (on-die bias LDOs and power good comparators for minimal power sequencing requirements consistent with low cost supply design)
The device is composed of the following main subsystems, across different domains of the SoC, among others:
- One dual-core 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz and up to 24K DMIPS (Dhrystone Million Instructions per Second)
- Two Microcontroller Units (MCU), based on dual-core Arm Cortex-R5F processor running at up to 1.0 GHz, up to 8K as per DM DMIPS
- Two Navigator Subsystems (NAVSS) for data movement and control
- One Device Management and Security Controller (DMSC)
The device provides a rich set of peripherals such as:
- General connectivity peripherals, including:
- One 12-bit general purpose Analog-to-Digital Converters (ADC)
- Ten Inter-Integrated Circuit (I2C) interfaces
- Two Improved Inter-Integrated Circuit (I3C) controllers
- Eleven master/slave Multichannel Serial Peripheral Interfaces (MCSPI)
- Twelve configurable Universal Asynchronous Receiver/Transmitter (UART) interfaces
- Ten General-Purpose Input/Output (GPIO) modules
- High-speed interfaces, including:
- Two Gigabit Ethernet Switch (CPSW) modules
- One Dual-Role-Device (DRD) Universal Serial Bus Subsystem (USBSS) with integrated PHY
- One Peripheral Component Interconnect express (PCIe) Gen3 subsystem
- One 4-Lane Serializer/Deserializer (SerDes)
- Flash memory interfaces, including:
- One Octal SPI (OSPI) or one HyperBus™
- One General Purpose Memory Controller (GPMC) with Error Location Module (ELM) and 8- or 16- bit-wide data bus width (supports parallel NOR or NAND FLASH devices)
- Two Multimedia Card/Secure Digital (MMCSD) controllers
- One Universal Flash Storage (UFS) interface
- Industrial and control interfaces, including:
- Twenty Controller Area Network (MCAN) interfaces with flexible data rate support
- Three Enhanced Capture (ECAP) modules
- Six Enhanced Pulse-Width Modulation (EPWM) subsystems
- Three Enhanced Quadrature Encoder Pulse (EQEP) modules
- Audio peripherals, including:
- One Audio Tracking Logic (ATL)
- Three Multichannel Audio Serial Port (MCASP) modules supporting up to 16 channels with independent TX/RX clock/sync domain
The device also integrates:
- Power distribution, reset controls and clock management components
- Power-management techniques for device power consumption minimization:
- Adaptive Voltage Scaling (AVS)
- Dynamic Frequency Scaling (DFS)
- Gated clocks
- Multiple voltage domains
- Independently controlled power domains for major modules
- Voltage and Temperature Management (VTM) module
- Power-on Reset Generators (PRG)
- Power Sleep Controllers (PSC)
- Optimized interconnect (CBASS) architecture to enable latency-critical real time network and IO applications
- Control modules (CTRL_MMRs) mainly associated with device top-level configurations such as:
- IO Pad and pin multiplexing configuration
- PLL control and associated High-Speed Dividers (HSDIV)
- Clock selection
- Analog function controls
- Multicore Shared Memory Controller (MSMC)
- DDR Subsystem (DDRSS) with Error Correcting Code (ECC), supporting LPDDR4
- 2KB RAM with ECC support for A72 and R5F boot vectors
- 512KB On-Chip SRAM protected by ECC
- One Global Time Counter (GTC) module
- Thirty 32-bit counter timers with compare and capture modes
- Debug and trace capabilities
The device includes different modules for functional safety requirements support:
- MCU island with Arm Cortex-R5F configured for split/lock operation
- Extended MCU (eMCU) for safety function processing
- Safety enabled interconnect with implemented features to help with Freedom From Interference (FFI)
- Six Windowed Watchdog Timers (WWDT) to monitor processor cores
- Ten Dual-Clock Comparators (DCC) to monitor clocking sources during run-time
- Three Error Signaling Modules (ESM) to enable error monitoring
- Temperature monitoring sensors
- ECC on all critical memories
- Dedicated hardware Memory Cyclic Redundancy Check (MCRC) blocks
The device supports the following main security functionalities among others:
- Secure Boot Management
- Public Key Accelerator (PKA) for large vector math operation
- Cryptographic acceleration (AES, 3DES, MD5, SHA1, SHA2-224, 256, 512 operation)
- Trusted Execution Environment (TEE)
- Secure storage support
- On-the-fly encryption and authentication support for OSPI interface
The device is partitioned into three functional domains, each containing specific processing cores and peripherals:
- Wake-up (WKUP) domain
- Microcontroller (MCU) domain
- MAIN domain (includes extended MCU)
This domain fragmentation enables the device to achieve lower power dissipation profiles by allowing the power supplies to unused domains to be completely turned off and allows efficient addressing of safety requirements.
Note:
The MCU and WKUP domains are combined into a common MCU/WKUP domain in this family of devices, but for compatibility with other K3 platform SoCs, the domain naming and separation are maintained throughout this document (where applicable).
1.2 Device Block Diagram
Figure 1-1 shows the DRA821 SoC top-level block diagram with domains partitions.
A. Both WKUP and MCU domain instances
are located on the MCU island but available for the full system to
access.
B. SGMII, USB3.0, and PCIE share
total of four SerDes lanes. A maximum of two of the three IP (for example, SGMII
and USB) can be used concurrently.
C. Flash interface can be configured
as OSPI0, or HyperBus.
D. One port is internally connected
only. Not connected to any pins.
E. A
solid black box indicates the IP is part of the Extended MCU (eMCU).
F. A
dashed black box indicates that some instances of the IP are present in the eMCU
and some instances are present in the non-eMCU portion of the Main
Domain.
Figure 1-1 Device Top-level Block
DiagramTable 1-1 shows device IPs allocation within device domains.
Table 1-1 Modules Allocation and Instances within Device Domains
| Module Full Name | Module Abbreviation | Domain | ||
|---|---|---|---|---|
| WKUP | MCU | MAIN | ||
| Dual-core Arm Cortex-A72 MPU | A72SS | - | - | 1 |
| Dual-core Arm Cortex-R5F Subsystem | R5FSS | - | 1 | 1 |
| Arm Cortex-M3 based Device Management Security Controller | DMSC | 1 | - | - |
| Mailbox | MAILBOX | - | - | 1 |
| Spinlock | SPINLOCK | - | - | 1 |
| Multicore Shared Memory Controller | MSMC | - | - | 1 |
| DDR Subsystem | DDRSS | - | - | 1 |
| Peripheral Virtualization Unit | PVU | - | - | 2 |
| Region-based Address Translation | RAT | 1 | 2 | 2 |
| Navigator Subsystem | NAVSS | - | 1 | 1 |
| Unified DMA Controller | UDMA | - | 1 | 1 |
| Ring Accelerator | RINGACC | - | 1 | 1 |
| Proxy | PROXY | - | 1 | 1 |
| Secure Proxy | SEC_PROXY | - | 1 | 1 |
| Interrupt Aggregator | INTR_AGGR | - | 1 | 3 |
| Peripheral Direct Memory Access | PDMA | - | 4 | 8 |
| Common Platform Time Sync Module | CPTS | - | 1 | 3 |
| Timer Manager | TIMER_MGR | - | - | 2 |
| Analog-to-Digital Converter | ADC | - | 1 | - |
| General-Purpose Input/Output | GPIO | 2 | - | 4 |
| Inter-Integrated Circuit | I2C | 1 | 2 | 7 |
| Improved Inter-Integrated Circuit | I3C | - | 1 | 1 |
| Multichannel Serial Peripheral Interface | MCSPI | - | 3 | 8 |
| Universal Asynchronous Receiver/Transmitter | UART | 1 | 1 | 10 |
| Gigabit Ethernet Switch | CPSW | - | 1 | 1 |
| Peripheral Component Interconnect Express | PCIe | - | - | 1 |
| Universal Serial Bus Subsystem | USBSS | - | - | 1 |
| Serializer/Deserializer | SERDES | - | - | 1 |
| Flash Memory Subsystem | FSS | - | 1 | - |
| Octal Serial Peripheral Interface | OSPI | - | 1 | - |
| HyperBus Interface | HPB | - | 1 | - |
| General-Purpose Memory Controller | GPMC | - | - | 1 |
| Error Location Module | ELM | - | - | 1 |
| Multimedia Card/Secure Digital Interface | MMCSD | - | - | 2 |
| Enhanced Capture Module | ECAP | - | - | 3 |
| Enhanced Pulse Width Modulation Module | EPWM | - | - | 6 |
| Enhanced Quadrature Encoder Pulse Module | EQEP | - | - | 3 |
| Controller Area Network Interface | MCAN | - | 2 | 18 |
| Audio Tracking Logic | ATL | - | - | 1 |
| Multichannel Audio Serial Port | MCASP | - | - | 3 |
| Global Timer Counter | GTC | - | - | 1 |
| Real Time Interrupt Windowed Watchdog Module | RTI | - | 2 | 4 |
| Timers | TIMER | - | 10 | 20 |
| Dual Clock Comparator | DCC | - | 3 | 7 |
| Error Signaling Module | ESM | 1 | 1 | 1 |
| Memory Cyclic Redundancy Check | MCRC | - | 1 | 1 |
Note:
The supported set of features and peripherals is device part number dependent. For more information, see the device-specific Datasheet.
1.3 Device Main Domain
This section describes the modules integrated in the device MAIN domain, including the extended MCU (eMCU) domain. eMCU domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4).
Figure 1-2 is a block diagram of the device MAIN domain.
Figure 1-2 Device Main Domain Block DiagramNote:
The supported set of features and peripherals is device part number dependent. For more information, see the device-specific Datasheet.
1.3.1 Arm Cortex-A72 Subsystem
The SoC implements one dual-core Arm Cortex-A72 Microprocessor Unit (MPU). Each core has the following main features:
- Full Armv8-A architecture compliancy
- Advanced Single Instruction Multiple Data (SIMD) and floating point extension (Arm Neon™)
- Armv8 cryptography extensions
- Superscalar, variable length, out-of-order pipeline
- 48KB program and 32KB data Level 1 (L1) Cache
- 1MB shared Level 2 (L2) Cache
- ECC protection for L1 data cache and L2 Cache
- Parity protection for L1 Instruction Cache
- Dynamic branch prediction with Branch Target Buffer (BTB) and Global History Buffer (GHB) RAMs, return stack, and indirect predictor
- Arm General Interrupt Controller (GICv3) architecture
- Support for up to four timers within each Cortex-A72 core
- 512-bit wide, synchronous or asynchronous VBUSM.C master interface
- Arm CoreSight™ Debug and Trace Architecture
- Advanced power management for low power optimization
- SoC level dedicated RTI windowed watchdog timer per core
1.3.2 Arm Cortex-R5F Processor
Integrated in MAIN domain in one instance of the dual-core Arm Cortex-R5F processor. Each dual-core instance supports the following main features:
- Armv7-R architecture
- Two modes of operation, boot-time configurable:
- Split mode: two independently operating cores (asymmetric multi processing, no coherence)
- Lock (lockstep) mode: one main operating core with the other operating in lockstep
- 32KB instruction and 32KB data SECDED ECC protected L1 cache per core
- 64KB of Tightly Coupled Memory (TCM) per core in a split mode
- 128KB of TCM for CPU0 in lock mode
- Full-Precision Floating Point (VFPv3)
- 8 breakpoints, 8 watch points
- 16-region Memory Protection Unit (MPU)
- CoreSight Debug Access Port (DAP)
- CoreSight ETM-R5 interface
- Performance Monitoring Unit (PMU)
- 32-bit to 48-bit Region-based Address Translation (RAT) on memory access masters
- Integrated Vectored Interrupt Manager (VIM)
- Interfaces:
- 64-bit VBUSM master pair (1 read, 1 write) for L3 memory accesses (per core)
- 64-bit VBUSM slave for TCM access (per core)
- 32-bit VBUSM master pair (1 read, 1 write) for peripheral access
- 32-bit VBUSP master for peripheral access (per core)
- 32-bit VBUSP slave configuration port (per core)
- 32-bit VBUSP slave debug port
1.3.3 Navigator Subsystem
Instantiated in the MAIN domain one Navigator subsystem named NAVSS can be used for efficient transfer of data support between software, firmware and hardware in all combinations. It consists of the following main modules:
- Unified DMA Controller with the following main modes and features:
- K3 DMA Architecture compliant Tx/Rx port implementation
- K3 DMA Architecture compliant Packet-Oriented DMA Functionality (UDMA-P)
- K3 DMA Architecture compliant Third Party Channel Controller
- K3 DMA Architecture compliant Unified Transfer Controller
- K3 DMA Architecture compliant Unified DMA channels which all share the execution hardware using time division multiplexing
- Ring Accelerator provides hardware acceleration to enable straightforward passing of work between a producer and a consumer and has the following main features:
- Supports 1024 independent memory-mapped ring structures
- Supports various modes for each ring based on usage and compatibility
- Provides 2-words deep shared incoming Transfer Response FIFO
- Provides bit-wide source VBUSM read/write slave interface for accesses from DMA controller entities
- Proxy module with the following main features:
- Provides proxy buffers to store large data bursts that a host can only access in smaller amounts
- Keeps the large data coherent until the complete data has been accessed
- Allows interleaved access between multiple hosts using multiple proxies
- Supports a pre-configured number of target resources to proxy with pre-configured number of channels, size of each channel, and address offset per each target
- Secure proxy module is a modified version of the proxy module and in addition has the following main features:
- Supports a number of threads, where each has their own independent proxy function
- Supports a programmable fixed queue for each proxy thread
- Supports multiple producers all writing to the same queue
- Supports programmable thresholds for when to generate events
- Supports a max message count for outbound proxy threads limiting the number of messages a thread can produce
- Interrupt Aggregator modules provide a centralized machine which handles the termination of system events to that they can be coherently processed by the host(s) in the system. Main features are as follows:
- 64-bit VBUSP slave using 64-bit registers
- Provide a set of TI Interrupt Architecture compliant interrupt status and mask registers which are used to pass specific event status to one or more host blocks.
- Provide a set of Global Event Input (GEVI) counters which can count events delivered via an ingress Event Transport Lane (ETL)
- Provides a set of Local Event Input (LEVI) to Global event registers which can be used to convert pulsed discrete interrupt inputs or clock synchronous rising edge events into Global events on an egress ETL
- Provides a set of GEVI 'Multicast' registers which can take a Global event from an ingress ETL and generate two egress Global events on two egress ETL interfaces
- Peripheral Virtualization Unit (PVU) module which provides TLBs (Translation Look-aside Buffers) for static virtual address translation on a CBA VBUSM bus with the following main features:
- Implements a channelized TLB for virtual address translation
- Supports a pre-configured number of entries per TLB channel
- Supports TLB chaining to extend the search but at a latency penalty
- Supports a 48-bit address size
- Supports page sizes of 4KB, 16KB, 64KB, 2MB, 32MB, 512MB, 1GB, and 16GB
- Support TLBs in software mode, where they are maintained by software only
- Produces a fault interrupt when the TLB misses or upon a permission error
- Mailbox module to facilitate the communication between the various on-chip processors of the device by providing a queued mailbox-interrupt mechanism with the following main features:
- 12 clusters
- 32-bit message width
- Message reception and queue-not-full notification using interrupts
- Non-intrusive emulation
- Spinlock module (256 hardware semaphores) for synchronizing the processes running on multiple processors in the device.
- Two Timer Manager modules to support timing operations for the processes running on multiple processors, each with the following main features:
- 1024 × 32-bit RAM-based independent timers (2048 in total)
- Event interface to an interrupt aggregation module in the NAVSS subsystem with events triggering when a timer expires or when an expired timer is reset or deactivated
- Host access to determine which timer(s) expired
- 32 registers with individual timeout status (one bit per timer)
- Groups of 16 timers separated into pages of 4-K address space
- Timer bits within each page to read expiration status for each timer when software only has access to that page
- 10 μs time to cycle through all of the timers
- Host access to reset individual timers
- Periodic hardware timers – a timer may be set to automatically reprogram itself upon expiration without software intervention.
- Three Time Sync modules to facilitate host control of time sync operations, each with the following main features:
- Supports a selection of multiple external clock sources
- Software control of time sync events via interrupt or polling
- Supports 8 hardware timestamp push inputs
- Supports timestamp counter compare output
- Supports timestamp counter bit output
- Supports 6 timestamp generator function outputs
- 32-bit and 64-bit timestamp modes
- Memory Cyclic Redundancy Check module used to perform CRC to verify the integrity of a memory system with the following main features:
- Four channels to perform background signature verification on any memory subsystem
- Data compression on 8-, 16-, 32-, and 64-bit data size
- Dedicated CRC value register per channel which contains the pre-determined CRC value
- Timed base event trigger from timer to initiate DMA data transfer
- Programmable 20-bit pattern counter per channel to count the number of data patterns for compression
- Three modes of operation: Auto, Semi-CPU, and Full-CPU
- Timeout interrupt generation if CRC is not performed within the time limit
- Per channel DMA request generation to initiate CRC value transfer
1.3.4 Region-based Address Translation Module
Integrated in MAIN domain two instances of RAT module perform a region based address translation of a 32-bit input address into a 48-bit output address. Each RAT module provides the following main features:
- 16 regions with dedicated registers for attributes configuration:
- Region base address
- Region size
- Translated base address
- Address translation for only enabled regions
- Region boundary crossing transactions error generation
