SPRACP7 October   2019 AM6526 , AM6528 , AM6546 , AM6548

 

  1.   AM65xx Time Synchronization Architecture
    1.     Trademarks
    2. 1 Introduction
    3. 2 AM65xx Time Sync Architecture
      1. 2.1 Functional Overview
      2. 2.2 Time Sync Components
        1. 2.2.1 TSR and CER
        2. 2.2.2 NAV_CPTS
        3. 2.2.3 DM_Timers and Timer Managers
        4. 2.2.4 PCIe With PTM
        5. 2.2.5 IEP Timers in ICSSGx
        6. 2.2.6 CPSW
        7. 2.2.7 GTC
    4. 3 Time-Synchronization Examples
      1. 3.1 AM65xx as the Time Master Server
      2. 3.2 Multi-Domain Time Synchronization Across PCIe Interconnect
      3. 3.3 Hand-Over and Recovery
    5. 4 Summary
    6. 5 References

2.2.5 IEP Timers in ICSSGx

Figure 6 shows sync and latch signals from the IEP timers within each of the ICSSG subsystems. The two IEP timers in each of the ICSSG support 16 comparison events and 16 latch events. All comparison and latch events are connected to the CER to allow flexible event triggering and latching across the ICSSG modules. Additionally, a subset of compare events are connected to the TSR to synchronize with other modules in the device.

spracp7-fig6-iep-timers.gifFigure 6. IEP Timers and Clock Selection