SPMU403 January   2026 LMK3H2104

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1Configuration Overview
    1. 1.1 LMK3H2104A0D Configuration Information
  4. 2Device Register Map
  5. 3Device Registers
  6. 4Revision History

1.1 LMK3H2104A0D Configuration Information

Table 1-1 Frequency Configuration
OTP PageOUT0 (MHz)OUT1 (MHz)OUT2 (MHz)OUT3 (MHz)REF0 (MHz)REF1 (MHz)
OTP Page 0

50

50

25

24

50

50

OTP Page 1

50

50

25

24

50

50

OTP Page 2

50

50

25

24

50

50

OTP Page 3

50

50

25

24

50

50

Table 1-2 I2C Configuration
OTP PageI2C Configuration
OTP Page 0

I2C Address: 0X68

1 Byte Register Addressing

OTP Page 1

I2C Address: 0X68

1 Byte Register Addressing

OTP Page 2

I2C Address: 0X68

1 Byte Register Addressing

OTP Page 3

I2C Address: 0X68

1 Byte Register Addressing

OTP Page 0

Table 1-3 GPI Settings, OTP Page 0
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0

GPI

Normal

Enabled

Disabled

GPI1

GPI

Normal

Enabled

Disabled

GPI2

Alternate OE, Alternate Mapping 1

Normal

Enabled

Disabled

Table 1-4 GPIO Settings, OTP Page 0
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0

Alternate OE, Alternate Mapping 1

Normal

Enabled

Disabled

GPIO1

GPI

Normal

Enabled

Disabled

Table 1-5 Input Settings, OTP Page 0
InputPowered Up/DownInput FormatInput Termination
IN_0

Powered Down

N/A (IN0 Unused)

None, DC

Table 1-6 Output Settings, OTP Page 0
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0

50

In-Phase LVCMOS

PATH1

Enabled

No OE Group

Disabled

OUT1

50

In-Phase LVCMOS

PATH1

EnabledNo OE GroupDisabled
OUT2

25

In-Phase LVCMOS

PATH1

EnabledNo OE GroupDisabled
OUT3

24

In-Phase LVCMOS

PATH0

EnabledNo OE GroupDisabled
REF0

50

N/A

PATH1

EnabledNo OE GroupDisabled
REF1

50

N/A

PATH1

EnabledNo OE GroupDisabled

OTP Page 1

Table 1-7 GPI Settings, OTP Page 1
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0

GPI

Normal

Enabled

Disabled

GPI1

GPI

Normal

Enabled

Disabled

GPI2

Alternate OE, Alternate Mapping 1

Normal

Enabled

Disabled

Table 1-8 GPIO Settings, OTP Page 1
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0

Alternate OE, Alternate Mapping 1

Normal

Enabled

Disabled

GPIO1

GPI

Normal

Enabled

Disabled

Table 1-9 Input Settings, OTP Page 1
InputPowered Up/DownInput FormatInput Termination
IN_0

Powered Down

N/A (IN0 Unused)

None, DC

Table 1-10 Output Settings, OTP Page 1
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0

50

In-Phase LVCMOS

PATH1

Enabled

No OE Group

Disabled

OUT1

50

In-Phase LVCMOS

PATH1

EnabledNo OE GroupDisabled
OUT2

25

In-Phase LVCMOS

PATH1

EnabledNo OE GroupDisabled
OUT3

24

In-Phase LVCMOS

PATH0

EnabledNo OE GroupDisabled
REF0

50

N/A

PATH1

EnabledNo OE GroupDisabled
REF1

50

N/A

PATH1

EnabledNo OE GroupDisabled

OTP Page 2

Table 1-11 GPI Settings, OTP Page 2
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0

GPI

Normal

Enabled

Disabled

GPI1

GPI

Normal

Enabled

Disabled

GPI2

Alternate OE, Alternate Mapping 1

Normal

Enabled

Disabled

Table 1-12 GPIO Settings, OTP Page 2
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0

Alternate OE, Alternate Mapping 1

Normal

Enabled

Disabled

GPIO1

GPI

Normal

Enabled

Disabled

Table 1-13 Input Settings, OTP Page 2
InputPowered Up/DownInput FormatInput Termination
IN_0

Powered Down

N/A (IN0 Unused)

None, DC

Table 1-14 Output Settings, OTP Page 2
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0

50

In-Phase LVCMOS

PATH1

Enabled

No OE Group

Disabled

OUT1

50

In-Phase LVCMOS

PATH1

EnabledNo OE GroupDisabled
OUT2

25

In-Phase LVCMOS

PATH1

EnabledNo OE GroupDisabled
OUT3

24

In-Phase LVCMOS

PATH0

EnabledNo OE GroupDisabled
REF0

50

N/A

PATH1

EnabledNo OE GroupDisabled
REF1

50

N/A

PATH1

EnabledNo OE GroupDisabled

OTP Page 3

Table 1-15 GPI Settings, OTP Page 3
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0

GPI

Normal

Enabled

Disabled

GPI1

GPI

Normal

Enabled

Disabled

GPI2

Alternate OE, Alternate Mapping 1

Normal

Enabled

Disabled

Table 1-16 GPIO Settings, OTP Page 3
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0

Alternate OE, Alternate Mapping 1

Normal

Enabled

Disabled

GPIO1

GPI

Normal

Enabled

Disabled

Table 1-17 Input Settings, OTP Page 3
InputPowered Up/DownInput FormatInput Termination
IN_0

Powered Down

N/A (IN0 Unused)

None, DC

Table 1-18 Output Settings, OTP Page 3
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0

50

In-Phase LVCMOS

PATH1

Enabled

No OE Group

Disabled

OUT1

50

In-Phase LVCMOS

PATH1

EnabledNo OE GroupDisabled
OUT2

25

In-Phase LVCMOS

PATH1

EnabledNo OE GroupDisabled
OUT3

24

In-Phase LVCMOS

PATH0

EnabledNo OE GroupDisabled
REF0

50

N/A

PATH1

EnabledNo OE GroupDisabled
REF1

50

N/A

PATH1

EnabledNo OE GroupDisabled